Alternatives and similar repositories for VexRiscv-CCOPI:

Users that are interested in VexRiscv-CCOPI are comparing it to the libraries listed below

• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• ucb-art / fft
  ☆20Updated 5 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆59Updated last year
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 3 years ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆39Updated 9 months ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆55Updated 4 years ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆62Updated this week
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆14Updated 4 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆28Updated 2 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆53Updated 4 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆85Updated 3 years ago
• ljgibbslf / basic_cache_core
  ☆25Updated 4 years ago
• plex1 / SpinalDev
  Docker Development Environment for SpinalHDL
  ☆19Updated 7 months ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆52Updated last week
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆18Updated 2 years ago
• pulp-platform / axi_spi_slave
  ☆25Updated 3 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆21Updated 4 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆53Updated 5 years ago
• akshaymdas / OpenLANE-SkyWater130-workshop
  This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…
  ☆22Updated 3 years ago
• RicardoNid / ChainsawOld
  ☆23Updated 2 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆37Updated 10 months ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆38Updated 5 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆51Updated 10 months ago
• JulianKemmerer / Drexel-ECEC575
  ☆19Updated 10 years ago
• zao111222333 / spinalhdl-online
  ☆24Updated last year
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆38Updated 4 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆42Updated 4 years ago