Alternatives and similar repositories for NyuziToolchain:

Users that are interested in NyuziToolchain are comparing it to the libraries listed below

• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆94Updated 5 years ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 7 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆100Updated 6 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 5 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 7 years ago
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆31Updated 9 years ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆56Updated 4 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆86Updated 5 months ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆119Updated 10 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆72Updated 5 years ago
• maidenone / ORGFXSoC
  An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)
  ☆72Updated 12 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 4 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 5 years ago
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆58Updated 7 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 7 months ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆85Updated 5 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 4 years ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 6 years ago
• dmpro2014 / fpga
  VHDL description of the custom Demolicious GPU. Built during a single semester at NTNU
  ☆35Updated 8 years ago
• LEAP-FPGA / leap-documentation
  ☆23Updated 8 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆34Updated 7 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆72Updated 5 months ago
• openrisc / or1k_marocchino
  OpenRISC processor IP core based on Tomasulo algorithm
  ☆31Updated 3 years ago