jbush001 / NyuziToolchain

Related projects ⓘ

Alternatives and complementary repositories for NyuziToolchain

• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 7 years ago
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆30Updated 9 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆92Updated 5 years ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆56Updated 4 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆54Updated 7 years ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 4 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆72Updated 5 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆99Updated 6 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆73Updated 5 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆123Updated 4 years ago
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆56Updated 7 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆58Updated 5 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆85Updated 2 months ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆102Updated 10 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆119Updated 10 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆79Updated last month
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆80Updated 3 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 2 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆84Updated last year
• maidenone / ORGFXSoC
  An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)
  ☆72Updated 12 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆33Updated 7 years ago
• ucb-bar / esp-llvm
  UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM
  ☆123Updated 3 years ago
• esperantotech / boom-template
  A template for building new projects/platforms using the BOOM core.
  ☆24Updated 5 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆65Updated 5 years ago