jbush001 / NyuziToolchainLinks
Port of LLVM/Clang C compiler to Nyuzi parallel processor architecture
☆65Updated 3 years ago
Alternatives and similar repositories for NyuziToolchain
Users that are interested in NyuziToolchain are comparing it to the libraries listed below
Sorting:
- Documentation for the BOOM processor☆47Updated 8 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆38Updated 10 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆105Updated 7 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Open Processor Architecture☆26Updated 9 years ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 5 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆151Updated last month
- TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…☆150Updated 9 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- A fork of the main Verilator project for development work. The changes here are in preparation for committing back to the main project.☆18Updated 11 years ago
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆202Updated 5 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM☆122Updated 4 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆168Updated this week
- A utility for Composing FPGA designs from Peripherals☆185Updated 11 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- RISC-V Frontend Server☆64Updated 6 years ago
- The OpenRISC 1000 architectural simulator☆77Updated 7 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆90Updated 6 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- Basic RISC-V CPU implementation in VHDL.☆172Updated 5 years ago
- A 32-bit RISC-V processor for mriscv project☆60Updated 8 years ago
- A Tiny Processor Core☆114Updated 5 months ago