Alternatives and similar repositories for NyuziToolchain

Users that are interested in NyuziToolchain are comparing it to the libraries listed below

• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆39Updated 10 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆106Updated 7 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 5 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆120Updated 11 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• maidenone / ORGFXSoC
  An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)
  ☆74Updated 13 years ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆61Updated 5 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆153Updated 3 weeks ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆76Updated 6 years ago
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆60Updated 8 years ago
• jeremybennett / verilator
  A fork of the main Verilator project for development work. The changes here are in preparation for committing back to the main project.
  ☆18Updated 11 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆91Updated 6 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 8 years ago
• cornell-brg / pymtl
  Python-based hardware modeling framework
  ☆245Updated 6 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆60Updated 6 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆176Updated 2 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 6 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆88Updated 4 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆67Updated 6 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆88Updated 3 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 4 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago