jbush001 / NyuziToolchainLinks
Port of LLVM/Clang C compiler to Nyuzi parallel processor architecture
☆64Updated 2 years ago
Alternatives and similar repositories for NyuziToolchain
Users that are interested in NyuziToolchain are comparing it to the libraries listed below
Sorting:
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆34Updated 10 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆102Updated 6 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 4 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)☆72Updated 13 years ago
- TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…☆149Updated 9 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- A 32-bit RISC-V processor for mriscv project☆59Updated 8 years ago
- A Tiny Processor Core☆110Updated 2 months ago
- Yet Another RISC-V Implementation☆97Updated last year
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- The OpenRISC 1000 architectural simulator☆76Updated 5 months ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM☆124Updated 4 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆146Updated last month
- A utility for Composing FPGA designs from Peripherals☆184Updated 9 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- A template for building new projects/platforms using the BOOM core.☆24Updated 6 years ago