meton-robean / deca
RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)
☆13Updated 5 years ago
Alternatives and similar repositories for deca:
Users that are interested in deca are comparing it to the libraries listed below
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 5 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆25Updated last week
- ☆21Updated 4 years ago
- ☆29Updated 3 weeks ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- Learn NVDLA by SOMNIA☆33Updated 5 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆34Updated 3 months ago
- ☆44Updated 5 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated last month
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆14Updated 5 years ago
- ☆33Updated last month
- ☆24Updated 8 months ago
- Ventus GPGPU ISA Simulator Based on Spike☆43Updated last week
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- ☆35Updated 4 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆23Updated 2 years ago
- ☆16Updated 5 years ago
- ☆8Updated last year
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆15Updated last year
- A simple cycle-accurate DaDianNao simulator☆13Updated 6 years ago
- ☆20Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆16Updated 3 weeks ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- agile hardware-software co-design☆46Updated 3 years ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆23Updated last year