HEAP-Lab-VT / ASIC-DEFLATE-for-memoryLinks
hardware (ASIC) DEFLATE designed for low-latency page-granularity memory compression and implemented in Chisel
☆14Updated last year
Alternatives and similar repositories for ASIC-DEFLATE-for-memory
Users that are interested in ASIC-DEFLATE-for-memory are comparing it to the libraries listed below
Sorting:
- agile hardware-software co-design☆52Updated 4 years ago
- ☆40Updated 8 months ago
- ☆38Updated last year
- ☆36Updated 4 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- ☆19Updated 6 years ago
- MLSys 2021 paper: MicroRec: efficient recommendation inference by hardware and data structure solutions☆19Updated 4 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- FRAME: Fast Roofline Analytical Modeling and Estimation☆39Updated 2 years ago
- ☆29Updated 4 years ago
- ☆108Updated last year
- Release of stream-specialization software/hardware stack.☆120Updated 2 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆58Updated 6 years ago
- A Toy-Purpose TPU Simulator☆19Updated last year
- Ventus GPGPU ISA Simulator Based on Spike☆49Updated 2 weeks ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆73Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆69Updated 4 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆62Updated 2 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- ☆28Updated 2 years ago
- ☆26Updated 2 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Updated 8 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 6 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆31Updated last week
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆81Updated 6 years ago
- ☆25Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆76Updated 3 months ago