LBL-CoDEx / OpenSoCFabricLinks
OpenSoC Fabric - A Network-On-Chip Generator
☆175Updated 5 years ago
Alternatives and similar repositories for OpenSoCFabric
Users that are interested in OpenSoCFabric are comparing it to the libraries listed below
Sorting:
- A Style Guide for the Chisel Hardware Construction Language☆109Updated 4 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆146Updated last year
- Chisel components for FPGA projects☆128Updated 2 years ago
- Network on Chip Implementation written in SytemVerilog☆198Updated 3 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆293Updated 3 months ago
- Examples for creating AXI-interfaced peripherals in Chisel☆75Updated 10 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Updated 6 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- A dynamic verification library for Chisel.☆160Updated last year
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- Vector processor for RISC-V vector ISA☆136Updated 5 years ago
- ☆88Updated 3 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆163Updated 2 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- Verilog Configurable Cache☆192Updated 2 weeks ago
- Comment on the rocket-chip source code☆179Updated 7 years ago
- A Chisel RTL generator for network-on-chip interconnects☆226Updated 3 months ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- An Open-Source Design and Verification Environment for RISC-V☆86Updated 4 years ago
- Public release☆58Updated 6 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆187Updated last year
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆37Updated 6 years ago
- Provides dot visualizations of chisel/firrtl circuits☆123Updated 2 years ago
- Various caches written in Verilog-HDL☆127Updated 10 years ago
- SystemC/TLM-2.0 Co-simulation framework☆264Updated 8 months ago
- A Fast, Low-Overhead On-chip Network☆267Updated 2 weeks ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆169Updated 2 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated last month
- ☆82Updated last year