jbush001 / ChiselGPULinks
Experiments with fixed function renderers and Chisel HDL
☆59Updated 6 years ago
Alternatives and similar repositories for ChiselGPU
Users that are interested in ChiselGPU are comparing it to the libraries listed below
Sorting:
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- For contributions of Chisel IP to the chisel community.☆67Updated last year
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 5 years ago
- SPIR-V fragment shader GPU core based on RISC-V☆42Updated 4 years ago
- Yet Another RISC-V Implementation☆98Updated last year
- Lipsi: Probably the Smallest Processor in the World☆88Updated last year
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- Demo SoC for SiliconCompiler.☆62Updated 2 weeks ago
- SoftCPU/SoC engine-V☆55Updated 7 months ago
- ☆38Updated 3 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Updated 12 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆111Updated 2 years ago
- The specification for the FIRRTL language☆62Updated last week
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- An open-source custom cache generator.☆34Updated last year
- RISC-V GPGPU☆35Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- ☆60Updated 4 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆48Updated 5 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago