yaozhaosh / chisel-aesLinks
Chisel implementation of AES
☆23Updated 5 years ago
Alternatives and similar repositories for chisel-aes
Users that are interested in chisel-aes are comparing it to the libraries listed below
Sorting:
- ☆80Updated last year
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- A dynamic verification library for Chisel.☆155Updated 11 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Chisel Learning Journey☆110Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆89Updated last year
- Provides various testers for chisel users☆99Updated 2 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- A prototype GUI for chisel-development☆51Updated 5 years ago
- Chisel components for FPGA projects☆126Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuits☆121Updated 2 years ago
- ☆33Updated 6 months ago
- ☆20Updated 5 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆115Updated 4 months ago
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 5 years ago
- ☆98Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- CVA6 SDK containing RISC-V tools and Buildroot☆74Updated 3 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆107Updated 4 months ago
- Useful utilities for BAR projects☆32Updated last year
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆63Updated 2 years ago
- ☆22Updated 4 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆66Updated last year
- ☆40Updated 4 months ago