Alternatives and similar repositories for chisel-aes:

Users that are interested in chisel-aes are comparing it to the libraries listed below

• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 3 years ago
• ucb-art / fft
  ☆20Updated 5 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆74Updated 9 years ago
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆26Updated last year
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆62Updated last year
• ucb-bar / sha3
  ☆80Updated last year
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆81Updated last year
• RPTU-EIS / upec-boom-verification-suite
  This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…
  ☆17Updated 2 years ago
• sequencer / arithmetic
  ☆33Updated last month
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 4 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆61Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 11 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆25Updated 4 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆58Updated last year
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆23Updated 6 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆56Updated last month
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 9 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated 2 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆45Updated last month
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated 11 months ago
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆20Updated 6 years ago
• oprecomp / DDR4_controller
  ☆55Updated 4 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆53Updated 3 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 5 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago