DreamCloud-Project / McSim-Cycle-accurate-NoCLinks
Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level
☆11Updated 7 years ago
Alternatives and similar repositories for McSim-Cycle-accurate-NoC
Users that are interested in McSim-Cycle-accurate-NoC are comparing it to the libraries listed below
Sorting:
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Updated 9 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆56Updated 8 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Updated 11 years ago
- Public release☆58Updated 6 years ago
- A parallel and distributed simulator for thousand-core chips☆27Updated 7 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last week
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- Documentation for the entire CGRAFlow☆19Updated 4 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆29Updated 2 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Updated 5 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 11 months ago
- DASS HLS Compiler☆29Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Project repo for the POSH on-chip network generator☆52Updated 10 months ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Updated 10 years ago
- RTL implementation of a ray-tracing GPU☆14Updated 13 years ago
- The official NaplesPU hardware code repository☆21Updated 6 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- Virtio implementation in SystemVerilog☆48Updated 7 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Updated 7 years ago
- Ratatoskr NoC Simulator☆29Updated 4 years ago
- ☆29Updated 8 years ago
- An infrastructure for integrated EDA☆42Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month