pulp-platform / hwpe-mac-engineLinks
An example Hardware Processing Engine
☆11Updated 2 years ago
Alternatives and similar repositories for hwpe-mac-engine
Users that are interested in hwpe-mac-engine are comparing it to the libraries listed below
Sorting:
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated 3 weeks ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- ☆27Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 11 months ago
- ☆53Updated 6 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆20Updated 2 years ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- Ratatoskr NoC Simulator☆28Updated 4 years ago
- DUTH RISC-V Microprocessor☆20Updated 9 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- SRAM☆22Updated 5 years ago
- ☆36Updated 6 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆31Updated 3 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- ☆29Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆58Updated 11 months ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 7 months ago
- eyeriss-chisel3☆41Updated 3 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆46Updated 3 years ago
- Parameterized Booth Multiplier in Verilog 2001☆50Updated 2 years ago
- CNN accelerator☆27Updated 8 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- Public release☆56Updated 6 years ago
- A repository for SystemC Learning examples☆70Updated 2 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆19Updated 6 months ago