An example Hardware Processing Engine
☆12Feb 4, 2023Updated 3 years ago
Alternatives and similar repositories for hwpe-mac-engine
Users that are interested in hwpe-mac-engine are comparing it to the libraries listed below
Sorting:
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated 2 months ago
- ☆13Jan 14, 2021Updated 5 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆23Jul 12, 2023Updated 2 years ago
- ☆11Feb 16, 2019Updated 7 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Mar 9, 2026Updated last week
- Reconfigurable Binary Engine☆17Mar 23, 2021Updated 4 years ago
- Development and simulation framework for Application Specific Vector Processor☆16Mar 8, 2020Updated 6 years ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Mar 9, 2026Updated last week
- calculate number of OPS (computation) in a Keras model!☆12Oct 26, 2020Updated 5 years ago
- RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo☆13Mar 7, 2020Updated 6 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated 3 weeks ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆25Jul 14, 2020Updated 5 years ago
- Neural Engine, 16 input channels☆16Oct 31, 2022Updated 3 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated this week
- [UNRELEASED] FP div/sqrt unit for transprecision☆27Sep 9, 2025Updated 6 months ago
- Dweb 2FA Client☆13Feb 16, 2024Updated 2 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆12Feb 22, 2018Updated 8 years ago
- VexRiscv-SMP integration test with LiteX.☆25Nov 16, 2020Updated 5 years ago
- ☆13Apr 6, 2021Updated 4 years ago
- RISC-V-based many-core neuromorphic architecture☆16Aug 3, 2025Updated 7 months ago
- Network on Chip for MPSoC☆28Feb 28, 2026Updated 3 weeks ago
- Video Effects on VGA☆15Jan 7, 2019Updated 7 years ago
- A vector graphics renderer for bgfx, based on ideas from NanoVG and ImDrawList (Dear ImGUI)☆10Feb 11, 2026Updated last month
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Aug 30, 2016Updated 9 years ago
- An Energy-Efficient Spiking Neural Network for Finger Velocity Decoding for Implantable Brain-Machine Interface☆12Apr 12, 2022Updated 3 years ago
- Toy RISC-V emulator☆15Oct 10, 2017Updated 8 years ago
- INT-Q Extension of the CMSIS-NN library for ARM Cortex-M target☆18Jan 10, 2020Updated 6 years ago
- FastFeedForward Networks☆20Dec 8, 2023Updated 2 years ago
- A Goldschmidt integer divider written in verilog. Similar to Newton-Raphson but the divison step can be pipelined.☆16Apr 25, 2024Updated last year
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆463May 15, 2025Updated 10 months ago
- pulp_soc is the core building component of PULP based SoCs☆83Mar 10, 2025Updated last year
- Demo of simulating kicad schematics in spice☆12Apr 30, 2015Updated 10 years ago
- An Open-Source Processor for Accelerating Spiking Neural Network☆12Sep 30, 2022Updated 3 years ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆14Mar 12, 2026Updated last week
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Mar 9, 2026Updated last week
- ☆13Feb 8, 2021Updated 5 years ago
- ☆25Apr 13, 2025Updated 11 months ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago