PeterAaser / tdt4255-chisel-introView external linksLinks
☆26Sep 3, 2020Updated 5 years ago
Alternatives and similar repositories for tdt4255-chisel-intro
Users that are interested in tdt4255-chisel-intro are comparing it to the libraries listed below
Sorting:
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 5 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Apr 18, 2022Updated 3 years ago
- This is my first trial project for designing RISC-V in Chisel☆17Apr 29, 2024Updated last year
- For contributions of Chisel IP to the chisel community.☆70Nov 7, 2024Updated last year
- Chisel components for FPGA projects☆128Sep 19, 2023Updated 2 years ago
- Bonfire SoC running on FireAnt FPGA Board☆12Feb 11, 2024Updated 2 years ago
- Wishbone to ARM AMBA 4 AXI☆16May 25, 2019Updated 6 years ago
- ☆11May 30, 2024Updated last year
- ☆10Dec 28, 2020Updated 5 years ago
- ☆15Mar 24, 2023Updated 2 years ago
- Uart module written in chisel☆13Feb 19, 2016Updated 9 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- A Style Guide for the Chisel Hardware Construction Language☆109Jul 16, 2021Updated 4 years ago
- Chisel Cheatsheet☆35Apr 13, 2023Updated 2 years ago
- Netrace: a network packet trace reader☆14Jun 16, 2014Updated 11 years ago
- A simple trace-based cache simulator☆16Jan 3, 2025Updated last year
- ☆18Oct 6, 2025Updated 4 months ago
- A C++ Library for Hardware Design and Simulation☆15May 17, 2020Updated 5 years ago
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Sep 5, 2019Updated 6 years ago
- CNN accelerator using NoC architecture☆17Dec 6, 2018Updated 7 years ago
- Floating point modules for CHISEL☆32Nov 2, 2014Updated 11 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 3 years ago
- 🎞️ NoC router in Verilog with FIFO☆16Sep 1, 2022Updated 3 years ago
- ☆18Jan 22, 2025Updated last year
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 11 years ago
- An executable specification of the RISCV ISA in L3.☆42Mar 1, 2019Updated 6 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆119Nov 10, 2025Updated 3 months ago
- Lab assignments for the Agile Hardware Design course☆18Nov 14, 2025Updated 2 months ago
- A tool for merging the MyHDL workflow with Vivado☆20May 13, 2020Updated 5 years ago
- A teaching-focused RISC-V CPU design used at UC Davis☆154Feb 5, 2023Updated 3 years ago
- Tests for example Rocket Custom Coprocessors☆75Feb 19, 2020Updated 5 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Jun 22, 2024Updated last year
- ☆19Dec 18, 2024Updated last year
- A collection of notes related to RISC-V before they are processed and digested☆18Dec 19, 2017Updated 8 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 3 years ago
- Code repo for efficient quantized MoE inference with mixture of low-rank compensators☆31Apr 14, 2025Updated 10 months ago
- Block-diagram style digital logic visualizer☆23Sep 16, 2015Updated 10 years ago
- SoftCPU/SoC engine-V☆55Mar 19, 2025Updated 10 months ago
- Open-source non-blocking L2 cache☆52Feb 3, 2026Updated last week