jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-EngineLinks
RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
☆22Updated 3 years ago
Alternatives and similar repositories for 64-bit-Universal-Floating-Point-ISA-Compute-Engine
Users that are interested in 64-bit-Universal-Floating-Point-ISA-Compute-Engine are comparing it to the libraries listed below
Sorting:
- ☆27Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated this week
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆30Updated last week
- Reconfigurable Binary Engine☆17Updated 4 years ago
- ☆10Updated last year
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- ☆14Updated 2 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- ☆21Updated 5 years ago
- SRAM☆22Updated 4 years ago
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- Approximate arithmetic circuits for FPGAs☆12Updated 5 years ago
- sram/rram/mram.. compiler☆37Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 10 months ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- CORE-V MCU UVM Environment and Test Bench☆21Updated last year
- APB Logic☆19Updated 7 months ago
- General Purpose AXI Direct Memory Access☆55Updated last year
- HLS for Networks-on-Chip☆35Updated 4 years ago
- SoC Based on ARM Cortex-M3☆32Updated 2 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆41Updated 2 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆15Updated this week
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆20Updated 11 months ago
- ☆29Updated 4 years ago