jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-EngineLinks
RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
☆22Updated 3 years ago
Alternatives and similar repositories for 64-bit-Universal-Floating-Point-ISA-Compute-Engine
Users that are interested in 64-bit-Universal-Floating-Point-ISA-Compute-Engine are comparing it to the libraries listed below
Sorting:
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- ☆27Updated 5 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- ☆15Updated 2 years ago
- ☆29Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆21Updated 5 years ago
- Approximate arithmetic circuits for FPGAs☆12Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆43Updated 5 years ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- Project repo for the POSH on-chip network generator☆50Updated 5 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- ☆21Updated 5 years ago
- ☆29Updated 3 weeks ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- ☆10Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆22Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆46Updated 3 years ago
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Updated 6 years ago
- SRAM☆23Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago