timurkelin / simsimdLinks
Development and simulation framework for Application Specific Vector Processor
☆13Updated 5 years ago
Alternatives and similar repositories for simsimd
Users that are interested in simsimd are comparing it to the libraries listed below
Sorting:
- Pulp virtual platform☆23Updated 2 years ago
- Userspace DMA library for Zynq-based SoCs☆16Updated 6 years ago
- Demonstration of Automatic Gain Control with PYNQ☆14Updated 2 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Updated 3 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆14Updated 2 weeks ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- SystemVerilog Logger☆17Updated 2 years ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated 2 weeks ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated 3 weeks ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆19Updated 2 years ago
- Open-Source HLS Examples for Microchip FPGAs☆44Updated last week
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated last week
- Chisel Things for OFDM☆32Updated 4 years ago
- ☆44Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 10 months ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 5 years ago
- ☆22Updated 3 weeks ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆17Updated 6 years ago
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆20Updated 6 months ago
- Parsing library for BLIF netlists☆19Updated 7 months ago
- Fault Injection Automatic Test Equipment☆14Updated 3 years ago
- XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA☆18Updated last year
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 5 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago