Alternatives and similar repositories for chisel2-deprecated

Users that are interested in chisel2-deprecated are comparing it to the libraries listed below

• stanford-ppl / spatial-lang
  Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
  ☆101Updated 6 years ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆747Updated last year
• inforichland / freezing-spice
  A pipelined RISCV implementation in VHDL
  ☆96Updated 6 years ago
• vmware-archive / cascade
  A Just-In-Time Compiler for Verilog from VMware Research
  ☆446Updated 4 years ago
• YosysHQ / arachne-pnr
  Place and route tool for FPGAs
  ☆424Updated 6 years ago
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆602Updated 2 years ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆172Updated last year
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆719Updated this week
• riscvarchive / riscv-wiki
  ☆250Updated 8 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 5 years ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆551Updated last week
• zhemao / ez8
  The Easy 8-bit Processor
  ☆183Updated 11 years ago
• google / bottlerocket
  ☆109Updated 6 years ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆215Updated 5 years ago
• dawsonjon / Chips-2.0
  FPGA Design Suite based on C to Verilog design flow.
  ☆245Updated 6 years ago
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆238Updated last year
• ucb-bar / esp-llvm
  UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM
  ☆125Updated 4 years ago
• asicguy / gplgpu
  GPL v3 2D/3D graphics engine in verilog
  ☆670Updated 11 years ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆736Updated 3 years ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆327Updated 3 years ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆609Updated 3 years ago
• stanford-ppl / spatial
  Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
  ☆282Updated last year
• f32c / f32c
  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
  ☆413Updated 2 months ago
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆972Updated last year
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆88Updated this week
• NetFPGA / netfpga
  NetFPGA 1G infrastructure and gateware
  ☆379Updated 6 years ago
• fabioperez / space-invaders-vhdl
  Space Invaders game implemented with VHDL
  ☆156Updated 9 years ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆154Updated last year