ujamjar / hardcaml-riscvLinks
RISC-V instruction set CPUs in HardCaml
☆15Updated 9 years ago
Alternatives and similar repositories for hardcaml-riscv
Users that are interested in hardcaml-riscv are comparing it to the libraries listed below
Sorting:
- HardCaml example designs☆18Updated 7 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- A Verilog parser for Haskell.☆36Updated 4 years ago
- firrtlator is a FIRRTL C++ library☆23Updated 9 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆30Updated this week
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆38Updated 4 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 9 years ago
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 8 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆54Updated 4 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆37Updated 2 months ago
- Multi-threaded 32-bit embedded core family.☆24Updated 13 years ago
- CHERI-RISC-V model written in Sail☆66Updated 5 months ago
- soap - Structural Optimisation of Arithmetic Programs☆24Updated 9 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 5 years ago
- A reimplementation of a tiny stack CPU☆85Updated 2 years ago
- Manythread RISC-V overlay for FPGA clusters☆38Updated 3 months ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 5 years ago
- An experimental System-on-Chip with a custom compiler toolchain.☆60Updated 5 years ago
- Iodine: Verifying Constant-Time Execution of Hardware☆15Updated 4 years ago
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆24Updated 8 years ago
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆17Updated 5 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3