ujamjar / hardcaml-riscvLinks
RISC-V instruction set CPUs in HardCaml
☆15Updated 9 years ago
Alternatives and similar repositories for hardcaml-riscv
Users that are interested in hardcaml-riscv are comparing it to the libraries listed below
Sorting:
- HardCaml example designs☆18Updated 7 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- A Verilog parser for Haskell.☆36Updated 4 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- An experimental System-on-Chip with a custom compiler toolchain.☆60Updated 5 years ago
- CHERI-RISC-V model written in Sail☆64Updated 2 months ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆29Updated 3 weeks ago
- LLVM JIT Cycle Accurate Simulator for HardCaml☆13Updated 8 years ago
- Manythread RISC-V overlay for FPGA clusters☆38Updated last week
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago
- Hardcaml Verification Tools☆12Updated 3 weeks ago
- A reimplementation of a tiny stack CPU☆85Updated last year
- The Antikernel operating system project☆122Updated 5 years ago
- Convert Verilog to a Hardcaml design☆17Updated 3 weeks ago
- A bit-serial CPU☆19Updated 5 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 9 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 5 years ago
- soap - Structural Optimisation of Arithmetic Programs☆23Updated 9 years ago
- Libre Silicon Compiler☆22Updated 4 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆56Updated 5 years ago
- Kansas Lava☆49Updated 5 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 8 years ago
- RISC-V BSV Specification☆21Updated 5 years ago
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆25Updated 7 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 4 years ago
- Yet Another Forth Core...☆72Updated 11 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆36Updated 6 months ago
- RISC-V XBitmanip Extension☆26Updated 6 years ago