ucb-bar / fpga-spartan6

Related projects: ⓘ

• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆35Updated 6 years ago
• embecosm / chiphack
  Repository and Wiki for Chip Hack events.
  ☆50Updated 3 years ago
• ArcaneNibble / yavhdl
  Yet Another VHDL tool
  ☆31Updated 7 years ago
• olofk / simple_spi
  SPI core
  ☆15Updated 4 years ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆38Updated 8 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 5 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆42Updated last year
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆54Updated 7 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆34Updated 2 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 6 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆77Updated 9 months ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆33Updated 5 months ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆57Updated 3 weeks ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆20Updated 5 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆53Updated this week
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆33Updated 8 months ago
• daveshah1 / flow-examples
  Misc open FPGA flow examples
  ☆8Updated 4 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• bluecmd / wb-axi
  Wishbone <-> AXI converters
  ☆11Updated 9 years ago
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆29Updated 4 years ago
• ueliem / literate-broccoli
  ☆26Updated this week
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆63Updated 2 years ago
• emeb / up5k_riscv
  There are many RISC V projects on iCE40. This one is mine.
  ☆13Updated 4 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆39Updated 5 months ago
• ArcaneNibble / project-chibi
  Altera MAX V bitstream documentation -- CLEANUP PENDING
  ☆19Updated 4 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆40Updated 6 months ago