ucb-bar / fpga-spartan6Links
Support for zScale on Spartan6 FPGAs
☆16Updated 9 years ago
Alternatives and similar repositories for fpga-spartan6
Users that are interested in fpga-spartan6 are comparing it to the libraries listed below
Sorting:
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆40Updated 9 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Cross compile FPGA tools☆22Updated 4 years ago
- SPI core☆15Updated 5 years ago
- ☆63Updated 6 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- Wishbone <-> AXI converters☆14Updated 10 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆17Updated 6 months ago
- IP cores for the FPGA Libre project☆12Updated 7 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Updated 5 years ago
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆19Updated 5 years ago
- DyRACT Open Source Repository☆16Updated 9 years ago
- Yosys Plugins☆21Updated 5 years ago
- Wishbone controlled I2C controllers☆49Updated 6 months ago
- Yet Another VHDL tool☆31Updated 8 years ago
- ChipTools is a utility to automate FPGA build and verification☆24Updated 3 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- A reimplementation of a tiny stack CPU☆83Updated last year
- Enigma in FPGA☆29Updated 6 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆35Updated 3 years ago
- HDL tools layer for OpenEmbedded☆17Updated 7 months ago
- Repository and Wiki for Chip Hack events.☆50Updated 3 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- iCE40 floorplan viewer☆24Updated 6 years ago
- Small footprint and configurable Inter-Chip communication cores☆58Updated last week