ucb-bar / fpga-spartan6Links
Support for zScale on Spartan6 FPGAs
☆15Updated 10 years ago
Alternatives and similar repositories for fpga-spartan6
Users that are interested in fpga-spartan6 are comparing it to the libraries listed below
Sorting:
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆41Updated 9 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Scripts to automate the process of building an image for the Xilinx PYNQ project. This repository is deprecated as its functionality is n…☆20Updated 8 years ago
- Yosys Plugins☆22Updated 6 years ago
- ☆42Updated 5 years ago
- Python-based Portable IP-core Synthesis Framework for FPGA-based Computing☆53Updated 9 years ago
- ☆63Updated 6 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago
- mirror of https://git.elphel.com/Elphel/vdt-plugin☆15Updated 7 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Updated 7 years ago
- OpenFPGA☆34Updated 7 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- SDSoC platforms for Digilent Zynq boards☆12Updated 8 years ago
- Sample minimal Vivado project for Parallella FPGA☆44Updated 9 years ago
- a playground for xilinx zynq fpga experiments☆49Updated 7 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- A collection of MyHDL cores and tools for complex digital circuit design☆86Updated 6 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- Adding PR to the PYNQ Overlay☆19Updated 8 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 9 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- Yet Another VHDL tool☆30Updated 8 years ago
- Repository of HW design and SW for Ultra96 board + MIPI board☆17Updated 6 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- SoftCPU/SoC engine-V☆55Updated 8 months ago