horie-t / homemade-riscv-enView external linksLinks
Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"
☆18Jul 30, 2019Updated 6 years ago
Alternatives and similar repositories for homemade-riscv-en
Users that are interested in homemade-riscv-en are comparing it to the libraries listed below
Sorting:
- Hardware design with Chisel☆35Feb 9, 2023Updated 3 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Space invaders hardware clone on the DE2-115 FPGA dev board with a USB keyboard and VGA output.☆13Feb 16, 2020Updated 6 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 6 years ago
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Jun 5, 2019Updated 6 years ago
- This repo contains source files and code for a synthesizable RISC-V processor with support for custom instructions in a co-processor.☆12Aug 19, 2018Updated 7 years ago
- High Throughput Image Filters on FPGAs☆14Oct 17, 2017Updated 8 years ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 10 years ago
- CNN accelerator using NoC architecture☆17Dec 6, 2018Updated 7 years ago
- An almost empty chisel project as a starting point for hardware design☆34Jan 27, 2025Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆18Nov 13, 2025Updated 3 months ago
- ☆16Apr 21, 2019Updated 6 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 5 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Mar 15, 2018Updated 7 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 5 years ago
- ☆24Aug 9, 2022Updated 3 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 3 years ago
- This is my first trial project for designing RISC-V in Chisel☆17Apr 29, 2024Updated last year
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆34Oct 23, 2025Updated 3 months ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- Another tiny RISC-V implementation☆64Jul 19, 2021Updated 4 years ago
- Provides various testers for chisel users☆100Jan 12, 2023Updated 3 years ago
- Building a busybox based RiscV 64-bit GNU/Linux system from scratch☆52Jun 13, 2019Updated 6 years ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆28Mar 3, 2024Updated last year
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55May 30, 2017Updated 8 years ago
- ☆30Mar 13, 2025Updated 11 months ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 2 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 5 months ago
- USB 2.0 Device IP Core☆74Oct 1, 2017Updated 8 years ago
- An implementation of RISC-V☆48Dec 11, 2025Updated 2 months ago
- DALI-based Driver for Mbed OS☆10Nov 28, 2018Updated 7 years ago