drom / reqack
🔁 elastic circuit toolchain
☆30Updated 2 months ago
Alternatives and similar repositories for reqack:
Users that are interested in reqack are comparing it to the libraries listed below
- 👾 Design ∪ Hardware☆74Updated 3 months ago
- FuseSoc Verification Automation☆22Updated 2 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- Debuggable hardware generator☆67Updated 2 years ago
- ☆22Updated last year
- A Verilog Synthesis Regression Test☆35Updated 11 months ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated 4 months ago
- ☆54Updated 2 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆59Updated 3 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 7 months ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Open Processor Architecture☆26Updated 8 years ago
- hardware library for hwt (= ipcore repo)☆36Updated 3 months ago
- Small footprint and configurable Inter-Chip communication cores☆55Updated last month
- mantle library☆42Updated 2 years ago
- ☆26Updated this week
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- chipy hdl☆17Updated 6 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆35Updated 3 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- OpenFPGA☆33Updated 6 years ago
- RISC-V processor☆28Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- The specification for the FIRRTL language☆51Updated this week
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 7 months ago