Alternatives and similar repositories for iodine

Users that are interested in iodine are comparing it to the libraries listed below

• ymanerka / rtlcheck
  RTLCheck
  ☆24Updated 7 years ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 5 years ago
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆14Updated 3 years ago
• comsec-group / cellift-yosys
  A fork of Yosys that integrates the CellIFT pass
  ☆13Updated 6 months ago
• daniellustig / pipecheck
  ☆19Updated 11 years ago
• daniellustig / coatcheck
  COATCheck
  ☆13Updated 7 years ago
• iscas-tis / CHA
  ☆19Updated last year
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆50Updated 2 weeks ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated 2 years ago
• ymanerka / pipeproof
  PipeProof
  ☆11Updated 6 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• yaohsiaopid / rtl2uspec
  ☆11Updated 7 months ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 8 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• efeslab / hardware-bugbase
  ☆20Updated last year
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆101Updated this week
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆36Updated 4 years ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆46Updated 4 months ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated 6 months ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated 2 years ago
• ics-jku / spinalfuzz
  Fuzzing for SpinalHDL
  ☆17Updated 3 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆23Updated 6 years ago
• comsec-group / encarsia
  ☆27Updated 10 months ago
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated 2 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆81Updated last year
• rsnikhil / Bluespec_BSV_Formal_Semantics
  Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
  ☆18Updated 9 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 6 months ago