Alternatives and similar repositories for iodine

Users that are interested in iodine are comparing it to the libraries listed below

• ymanerka / rtlcheck
  RTLCheck
  ☆22Updated 6 years ago
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• daniellustig / coatcheck
  COATCheck
  ☆13Updated 6 years ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 4 years ago
• ymanerka / pipeproof
  PipeProof
  ☆11Updated 5 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆46Updated 2 weeks ago
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆14Updated 3 years ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 4 years ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆81Updated this week
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 2 months ago
• iscas-tis / CHA
  ☆19Updated last year
• efeslab / hardware-bugbase
  ☆18Updated last year
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆37Updated 4 years ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆42Updated last week
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated 2 years ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated 2 months ago
• yaohsiaopid / rtl2uspec
  ☆11Updated 2 months ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆21Updated 5 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆34Updated 3 years ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆77Updated last year
• sterin / super-prove-build
  ☆13Updated 4 years ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated last month
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆23Updated 4 years ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆64Updated 2 months ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• rsnikhil / Bluespec_BSV_Formal_Semantics
  Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
  ☆18Updated 9 years ago