openhwgroup / cv-hpdcache
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
☆58Updated last week
Related projects ⓘ
Alternatives and complementary repositories for cv-hpdcache
- A Fast, Low-Overhead On-chip Network☆134Updated 2 weeks ago
- Advanced Architecture Labs with CVA6☆48Updated 9 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆90Updated this week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆57Updated 3 weeks ago
- ☆73Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆43Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 7 months ago
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated 2 weeks ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆103Updated this week
- Vector processor for RISC-V vector ISA☆109Updated 4 years ago
- General Purpose AXI Direct Memory Access☆44Updated 5 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated this week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆140Updated last year
- Pure digital components of a UCIe controller☆47Updated this week
- BlackParrot on Zynq☆25Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆60Updated 7 months ago
- Chisel RISC-V Vector 1.0 Implementation☆50Updated this week
- HLS for Networks-on-Chip☆30Updated 3 years ago
- Unit tests generator for RVV 1.0☆59Updated 3 weeks ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆47Updated 4 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 3 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆75Updated this week
- ☆46Updated 3 years ago
- RISC-V Verification Interface☆74Updated 2 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 5 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆94Updated last year
- ☆12Updated this week