openhwgroup / cv-hpdcacheLinks
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
☆92Updated 2 months ago
Alternatives and similar repositories for cv-hpdcache
Users that are interested in cv-hpdcache are comparing it to the libraries listed below
Sorting:
- A Fast, Low-Overhead On-chip Network☆231Updated last week
- Advanced Architecture Labs with CVA6☆68Updated last year
- ☆99Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆184Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago
- Vector processor for RISC-V vector ISA☆129Updated 5 years ago
- RISC-V Verification Interface☆108Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆142Updated last week
- BlackParrot on Zynq☆48Updated this week
- General Purpose AXI Direct Memory Access☆60Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 11 months ago
- An AXI4 crossbar implementation in SystemVerilog☆176Updated last month
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆122Updated 2 weeks ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆89Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆67Updated last month
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆17Updated this week
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆217Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 3 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆70Updated 4 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- A dynamic verification library for Chisel.☆156Updated 11 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆131Updated 7 years ago
- RISC-V System on Chip Template☆159Updated 2 months ago
- Verilog Configurable Cache☆184Updated 2 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- ☆67Updated 4 years ago