RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
☆103Mar 19, 2026Updated last month
Alternatives and similar repositories for cv-hpdcache
Users that are interested in cv-hpdcache are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆24Jan 6, 2026Updated 3 months ago
- The multi-core cluster of a PULP system.☆113Mar 28, 2026Updated 3 weeks ago
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated 8 months ago
- ☆34Feb 17, 2026Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 9 months ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A Fast, Low-Overhead On-chip Network☆280Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆145Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆130Jul 11, 2025Updated 9 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆328Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆204Apr 8, 2026Updated last week
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- ☆25Apr 12, 2026Updated last week
- Generic Register Interface (contains various adapters)☆138Feb 24, 2026Updated last month
- ☆14Jun 7, 2021Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- SystemVerilog Linter based on pyslang☆32May 5, 2025Updated 11 months ago
- Simple runtime for Pulp platforms☆52Feb 2, 2026Updated 2 months ago
- A reliable, real-time subsystem for the Carfield SoC☆20Dec 2, 2025Updated 4 months ago
- SystemVerilog file list pruner☆18Mar 2, 2026Updated last month
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆318Updated this week
- ☆135Aug 14, 2025Updated 8 months ago
- A Rocket-based RISC-V superscalar in-order core☆38Mar 11, 2026Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆661Apr 7, 2026Updated last week
- Administrative repository for the Integrated Matrix Extension Task Group☆36Dec 15, 2025Updated 4 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆505Apr 10, 2026Updated last week
- A Heterogeneous GPU Platform for Chipyard SoC☆50Apr 3, 2026Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,546Apr 11, 2026Updated last week
- ☆15Mar 9, 2026Updated last month
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,895Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆591Apr 7, 2026Updated last week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆220Mar 25, 2026Updated 3 weeks ago
- Coverview☆28Jan 29, 2026Updated 2 months ago
- RISC-V SIMD Superscalar Dual-Issue Processor☆29Apr 24, 2025Updated 11 months ago
- Deploy open-source AI quickly and easily - Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Chisel RISC-V Vector 1.0 Implementation☆143Apr 10, 2026Updated last week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,166Feb 21, 2026Updated last month
- Common SystemVerilog components☆736Updated this week
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆258Updated this week
- A Linux-capable RISC-V multicore for and by the world☆794Apr 8, 2026Updated last week
- The official NaplesPU hardware code repository☆24Jul 27, 2019Updated 6 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆216Apr 3, 2026Updated 2 weeks ago