openhwgroup / cv-hpdcacheLinks
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
☆94Updated last week
Alternatives and similar repositories for cv-hpdcache
Users that are interested in cv-hpdcache are comparing it to the libraries listed below
Sorting:
- A Fast, Low-Overhead On-chip Network☆247Updated this week
- ☆110Updated 3 weeks ago
- Advanced Architecture Labs with CVA6☆71Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆189Updated 2 months ago
- BlackParrot on Zynq☆47Updated 2 weeks ago
- Vector processor for RISC-V vector ISA☆130Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 3 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆125Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated last week
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 2 weeks ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆182Updated last year
- ☆32Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆59Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- ☆20Updated 3 weeks ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆124Updated last week
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆138Updated 7 years ago
- A dynamic verification library for Chisel.☆158Updated last year
- Network on Chip Implementation written in SytemVerilog☆194Updated 3 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last week
- This is the fork of CVA6 intended for PULP development.☆22Updated last week
- RISC-V Verification Interface☆126Updated 2 weeks ago
- SystemVerilog Functional Coverage for RISC-V ISA☆32Updated 6 months ago