RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
☆108May 22, 2026Updated last month
Alternatives and similar repositories for cv-hpdcache
Users that are interested in cv-hpdcache are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆26Jan 6, 2026Updated 6 months ago
- The multi-core cluster of a PULP system.☆114Jun 29, 2026Updated 2 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆163Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- ☆35Jul 2, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆355Updated this week
- A Fast, Low-Overhead On-chip Network☆319Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆225Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆136Jul 11, 2025Updated last year
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- ☆36Jun 25, 2026Updated 2 weeks ago
- Generic Register Interface (contains various adapters)☆140Jul 2, 2026Updated last week
- ☆16May 25, 2026Updated last month
- Simple runtime for Pulp platforms☆53Jul 7, 2026Updated last week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A reliable, real-time subsystem for the Carfield SoC☆21Dec 2, 2025Updated 7 months ago
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆321Jul 2, 2026Updated last week
- SystemVerilog file list pruner☆18Mar 2, 2026Updated 4 months ago
- ☆143Jun 8, 2026Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆673Jul 7, 2026Updated last week
- A Rocket-based RISC-V superscalar in-order core☆41Jul 3, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,621Updated this week
- A Heterogeneous GPU Platform for AI and Neural Graphics☆61Jun 22, 2026Updated 3 weeks ago
- Administrative repository for the Integrated Matrix Extension Task Group☆36Apr 25, 2026Updated 2 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,014Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆531Jun 8, 2026Updated last month
- ☆16May 6, 2026Updated 2 months ago
- Common SystemVerilog components☆764Jul 3, 2026Updated last week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆622Jul 2, 2026Updated last week
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆21Oct 22, 2025Updated 8 months ago
- Coverview☆31Jun 3, 2026Updated last month
- RISC-V SIMD Superscalar Dual-Issue Processor☆30Apr 24, 2025Updated last year
- Functional verification project for the CORE-V family of RISC-V cores.☆697Jun 22, 2026Updated 3 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆251Jun 30, 2026Updated 2 weeks ago
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆284Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆152Apr 23, 2026Updated 2 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆235Jun 20, 2026Updated 3 weeks ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,186Updated this week
- A Linux-capable RISC-V multicore for and by the world☆820Updated this week
- SystemVerilog (IEEE 1800-2017) Simulator☆60Updated this week