ucb-bar / constellationLinks
A Chisel RTL generator for network-on-chip interconnects
☆198Updated last month
Alternatives and similar repositories for constellation
Users that are interested in constellation are comparing it to the libraries listed below
Sorting:
- A dynamic verification library for Chisel.☆151Updated 6 months ago
- A Fast, Low-Overhead On-chip Network☆208Updated last week
- An AXI4 crossbar implementation in SystemVerilog☆156Updated 3 weeks ago
- Network on Chip Implementation written in SytemVerilog☆178Updated 2 years ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆231Updated 9 months ago
- ☆159Updated last month
- Vector processor for RISC-V vector ISA☆120Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 6 months ago
- Verilog Configurable Cache☆178Updated 6 months ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆154Updated last year
- A Library of Chisel3 Tools for Digital Signal Processing☆236Updated last year
- Pure digital components of a UCIe controller☆63Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆129Updated last week
- Vector Acceleration IP core for RISC-V*☆178Updated 3 weeks ago
- Wrapper for Rocket-Chip on FPGAs☆134Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆160Updated last week
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆269Updated last month
- Instruction Set Generator initially contributed by Futurewei☆284Updated last year
- Advanced Interface Bus (AIB) die-to-die hardware open source☆138Updated 8 months ago
- ☆326Updated 8 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆258Updated this week
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆126Updated 7 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆192Updated 4 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆100Updated last year
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆201Updated this week
- SystemC/TLM-2.0 Co-simulation framework☆247Updated 2 weeks ago
- RISC-V Torture Test☆195Updated 10 months ago
- Various caches written in Verilog-HDL☆124Updated 10 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆254Updated 3 months ago