ucb-bar / compress-acc
☆10Updated 3 months ago
Related projects ⓘ
Alternatives and complementary repositories for compress-acc
- ☆31Updated last month
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆55Updated 2 weeks ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- A Rocket-based RISC-V superscalar in-order core☆28Updated 3 weeks ago
- sram/rram/mram.. compiler☆29Updated last year
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆52Updated 2 weeks ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated 3 weeks ago
- Wrappers for open source FPU hardware implementations.☆31Updated 7 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆19Updated this week
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 4 years ago
- Chisel Cheatsheet☆31Updated last year
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆36Updated 2 months ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆26Updated 5 years ago
- ☆75Updated 2 years ago
- Chisel RISC-V Vector 1.0 Implementation☆54Updated this week
- ☆14Updated 2 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated this week
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆49Updated 4 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- CNN accelerator☆26Updated 7 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago