ucb-bar / compress-accLinks
☆14Updated 3 months ago
Alternatives and similar repositories for compress-acc
Users that are interested in compress-acc are comparing it to the libraries listed below
Sorting:
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated this week
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated last week
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- ☆30Updated 2 months ago
- A Rocket-based RISC-V superscalar in-order core☆34Updated last month
- ☆65Updated last week
- ☆33Updated 3 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆39Updated 2 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated last month
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆25Updated last week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- sram/rram/mram.. compiler☆35Updated last year
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆35Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆19Updated last month
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆21Updated 4 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆41Updated last month
- Reconfigurable Binary Engine☆17Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated last week
- HLS for Networks-on-Chip☆35Updated 4 years ago