ucb-bar / compress-acc
☆11Updated 5 months ago
Alternatives and similar repositories for compress-acc:
Users that are interested in compress-acc are comparing it to the libraries listed below
- ☆33Updated 3 years ago
- ☆21Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 4 years ago
- ☆32Updated this week
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆32Updated 4 years ago
- HLS for Networks-on-Chip☆33Updated 3 years ago
- CNN accelerator☆27Updated 7 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- ☆24Updated 5 years ago
- ☆40Updated 5 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆18Updated 4 months ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆17Updated 11 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆23Updated last year
- Provides dot visualizations of chisel/firrtl circuites☆12Updated 5 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆22Updated 3 months ago
- ☆14Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆49Updated 3 years ago
- ☆25Updated 11 months ago
- DUTH RISC-V Superscalar Microprocessor☆29Updated 3 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆15Updated 4 months ago
- FPU Generator☆20Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆27Updated 3 months ago
- CNN accelerator using NoC architecture☆15Updated 6 years ago
- Original test vector of RISC-V Vector Extension☆11Updated 3 years ago