Alternatives and similar repositories for vicuna

Users that are interested in vicuna are comparing it to the libraries listed below

• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆121Updated 4 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆204Updated 2 months ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆201Updated 2 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆97Updated last month
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆179Updated 7 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆215Updated this week
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆181Updated 3 weeks ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆289Updated last year
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆170Updated 7 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆140Updated 5 years ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆148Updated 5 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆181Updated last year
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated last month
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆185Updated 2 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆152Updated 8 months ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆91Updated this week
• chipsalliance / VeeR-ISS
  ☆139Updated last year
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆87Updated 4 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆169Updated 3 weeks ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 4 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆112Updated this week
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆180Updated 2 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆441Updated last week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆71Updated last year
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆262Updated last month
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆171Updated 7 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆161Updated last month
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆88Updated 2 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆123Updated last month
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 7 months ago