RISC-V Zve32x Vector Coprocessor
☆221Jan 22, 2026Updated 7 months ago
Alternatives and similar repositories for vicuna
Users that are interested in vicuna are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆539Aug 19, 2026Updated last week
- Vector processor for RISC-V vector ISA☆145Oct 19, 2020Updated 5 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- Andes Vector Extension support added to riscv-dv☆19May 29, 2020Updated 6 years ago
- matrix-coprocessor for RISC-V☆37Feb 27, 2026Updated 6 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆21Updated this week
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆105Aug 14, 2026Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,279Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆93Apr 1, 2026Updated 4 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆167Updated this week
- A matrix extension proposal for AI applications under RISC-V architecture☆187Apr 1, 2026Updated 4 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆262Aug 18, 2026Updated last week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆632Jul 24, 2026Updated last month
- Chisel RISC-V Vector 1.0 Implementation☆157Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆67Dec 19, 2021Updated 4 years ago
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆93Mar 26, 2023Updated 3 years ago
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,031Aug 20, 2026Updated last week
- ☆97Oct 18, 2023Updated 2 years ago
- A simple superscalar out-of-order RISC-V microprocessor☆254Feb 24, 2025Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆191Apr 4, 2026Updated 4 months ago
- Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions☆16Jan 21, 2026Updated 7 months ago
- VeeR EL2 Core☆344Updated this week
- 64-bit multicore Linux-capable RISC-V processor☆120Apr 28, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆229Nov 22, 2023Updated 2 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆422Updated this week
- Simple 3-stage pipeline RISC-V processor☆150Feb 24, 2026Updated 6 months ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆235Aug 24, 2026Updated last week
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆154Aug 14, 2026Updated 2 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆278Nov 6, 2024Updated last year
- GEMM and GEMM-Ops accelerator for PULP systems☆115Aug 5, 2026Updated 3 weeks ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆365Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A Linux-capable RISC-V multicore for and by the world☆827Jul 13, 2026Updated last month
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,087Updated this week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆39May 20, 2026Updated 3 months ago
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆34Updated this week
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆22Dec 10, 2022Updated 3 years ago