qleenju / PDPULinks
PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
☆43Updated 2 years ago
Alternatives and similar repositories for PDPU
Users that are interested in PDPU are comparing it to the libraries listed below
Sorting:
- ☆89Updated last week
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆75Updated 3 weeks ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆94Updated 11 months ago
- The Verilog source code for DRUM approximate multiplier.☆32Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 3 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- ☆28Updated 6 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last year
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- CNN accelerator☆28Updated 8 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Updated 2 years ago
- Project repo for the POSH on-chip network generator☆52Updated 9 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 6 months ago
- SRAM☆22Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆60Updated 8 months ago
- Floating point modules for CHISEL☆32Updated 11 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- sram/rram/mram.. compiler☆43Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- SpinalHDL Hardware Math Library☆93Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago