qleenju / PDPU
PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
☆39Updated last year
Alternatives and similar repositories for PDPU:
Users that are interested in PDPU are comparing it to the libraries listed below
- For contributions of Chisel IP to the chisel community.☆59Updated 4 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- ☆50Updated this week
- PACoGen: Posit Arithmetic Core Generator☆69Updated 5 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆29Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 3 months ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated last month
- HLS for Networks-on-Chip☆33Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆48Updated 2 months ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 6 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- An energy-efficient RISC-V floating-point compute cluster.☆70Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 6 months ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- SystemVerilog frontend for Yosys☆81Updated last week
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆87Updated 5 years ago
- ☆57Updated last year
- A configurable SRAM generator☆47Updated 2 months ago
- SRAM☆21Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- A tool to generate optimized hardware files for univariate functions.☆27Updated 11 months ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated last month
- ☆86Updated last year
- ☆17Updated 7 years ago
- ☆40Updated 3 months ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- Project repo for the POSH on-chip network generator☆44Updated last week