qleenju / PDPU
PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
☆37Updated last year
Alternatives and similar repositories for PDPU:
Users that are interested in PDPU are comparing it to the libraries listed below
- For contributions of Chisel IP to the chisel community.☆59Updated 3 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- PACoGen: Posit Arithmetic Core Generator☆68Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 2 months ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- ☆54Updated 2 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 5 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆58Updated last year
- Universal number Posit HDL Arithmetic Architecture generator☆55Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 3 months ago
- Floating point modules for CHISEL☆31Updated 10 years ago
- ☆15Updated 3 years ago
- SystemVerilog frontend for Yosys☆74Updated this week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated 4 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- 👾 Design ∪ Hardware☆74Updated 3 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 5 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated 3 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- Basic floating-point components for RISC-V processors☆64Updated 5 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 8 months ago
- Open source RTL simulation acceleration on commodity hardware☆23Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last week
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆29Updated last year
- ☆36Updated 2 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆72Updated 2 weeks ago
- An open source generator for standard cell based memories.☆13Updated 8 years ago