rivosinc / hammerLinks
Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
☆39Updated 3 weeks ago
Alternatives and similar repositories for hammer
Users that are interested in hammer are comparing it to the libraries listed below
Sorting:
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- The multi-core cluster of a PULP system.☆111Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- pulp_soc is the core building component of PULP based SoCs☆82Updated 11 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 7 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆136Updated this week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Updated this week
- Simple runtime for Pulp platforms☆50Updated last week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- RISC-V Nox core☆71Updated 6 months ago
- ☆90Updated last week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 4 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆195Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆111Updated 4 months ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆73Updated last year
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 2 months ago
- ☆89Updated 5 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆117Updated last year
- RISC-V Verification Interface☆138Updated 2 weeks ago
- A RISC-V Core (RV32I) written in Chisel HDL☆107Updated last week
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆109Updated 4 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆154Updated last year
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- A Tiny Processor Core☆114Updated 6 months ago
- Generic Register Interface (contains various adapters)☆135Updated 2 months ago
- Chisel RISC-V Vector 1.0 Implementation☆131Updated 4 months ago