rivosinc / hammerLinks
Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
☆39Updated 3 months ago
Alternatives and similar repositories for hammer
Users that are interested in hammer are comparing it to the libraries listed below
Sorting:
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆125Updated this week
- The multi-core cluster of a PULP system.☆109Updated last month
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 4 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆76Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- ☆88Updated last week
- Simple runtime for Pulp platforms☆49Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆189Updated 2 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- For contributions of Chisel IP to the chisel community.☆68Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆71Updated last year
- Chisel RISC-V Vector 1.0 Implementation☆121Updated 2 months ago
- ☆65Updated this week
- A Tiny Processor Core☆114Updated 4 months ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 2 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last week
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆107Updated 2 months ago
- A RISC-V Core (RV32I) written in Chisel HDL☆104Updated 2 weeks ago
- RTL data structure☆54Updated 3 months ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- The specification for the FIRRTL language☆62Updated last week
- ☆89Updated 3 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆151Updated last year