rivosinc / hammerLinks
Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
☆35Updated 2 years ago
Alternatives and similar repositories for hammer
Users that are interested in hammer are comparing it to the libraries listed below
Sorting:
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆113Updated this week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆63Updated 6 months ago
- The multi-core cluster of a PULP system.☆105Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆88Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 months ago
- RISC-V Nox core☆66Updated last week
- pulp_soc is the core building component of PULP based SoCs☆80Updated 4 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆72Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- Simple runtime for Pulp platforms☆48Updated last week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆171Updated 2 weeks ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆59Updated 8 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- Simple UVM environment for experimenting with Verilator.☆23Updated 3 months ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- A Rocket-based RISC-V superscalar in-order core☆34Updated 3 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆69Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆83Updated 9 months ago
- ☆52Updated 2 weeks ago
- RISC-V Verification Interface☆99Updated 2 months ago
- ☆71Updated last week
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆30Updated 2 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆24Updated 6 years ago