tum-ei-eda / muriscv-nnLinks
muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.
☆88Updated last month
Alternatives and similar repositories for muriscv-nn
Users that are interested in muriscv-nn are comparing it to the libraries listed below
Sorting:
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆88Updated 2 years ago
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆34Updated last week
- ☆86Updated 2 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆155Updated 9 months ago
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆43Updated 4 years ago
- RiVEC Bencmark Suite☆123Updated 11 months ago
- DNN Compiler for Heterogeneous SoCs☆53Updated last week
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆110Updated 2 years ago
- An optimized neural network operator library for chips base on Xuantie CPU.☆96Updated last year
- ☆87Updated this week
- PyTorch model to RTL flow for low latency inference☆130Updated last year
- Chisel RISC-V Vector 1.0 Implementation☆118Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆43Updated 5 months ago
- A tool to deploy Deep Neural Networks on PULP-based SoC's☆90Updated 3 months ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆35Updated last year
- ☆105Updated last year
- A scalable High-Level Synthesis framework on MLIR☆282Updated last year
- A DSL for Systolic Arrays☆82Updated 6 years ago
- ☆46Updated 5 years ago
- LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V☆23Updated 2 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆123Updated last week
- ☆54Updated 6 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆204Updated 5 years ago
- Learn NVDLA by SOMNIA☆42Updated 5 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆58Updated last month
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆78Updated last month
- ☆36Updated 7 months ago
- upstream: https://github.com/RALC88/gem5☆33Updated 2 years ago
- Unit tests generator for RVV 1.0☆94Updated last month