Alternatives and similar repositories for muriscv-nn:

Users that are interested in muriscv-nn are comparing it to the libraries listed below

• pulp-platform / pulp-nn
  ☆81Updated last year
• ucb-bar / onnxruntime-riscv
  Fork of upstream onnxruntime focused on supporting risc-v accelerators
  ☆83Updated last year
• tum-ei-eda / mlonmcu
  Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends
  ☆33Updated last week
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆128Updated last month
• pulp-platform / dory
  A tool to deploy Deep Neural Networks on PULP-based SoC's
  ☆80Updated 3 weeks ago
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆212Updated 2 years ago
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆94Updated last year
• compiler-dev / llvm-rv
  Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
  ☆43Updated 4 years ago
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆250Updated 9 months ago
• zeasa / nvdla-compiler
  ☆42Updated 5 years ago
• Xilinx / mlir-air
  ☆90Updated this week
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated last year
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆125Updated 11 months ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• riscv-stc / riscv-matrix-project
  Top project for RISC-V Matrix extension proposal and related opensource implementations.
  ☆28Updated 11 months ago
• vortexgpgpu / vortex_tutorials
  ☆158Updated last month
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆184Updated 4 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆48Updated last week
• THU-DSP-LAB / ventus-gpgpu-isa-simulator
  Ventus GPGPU ISA Simulator Based on Spike
  ☆42Updated 3 weeks ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆130Updated 2 months ago
• pulp-platform / Deeploy
  DNN Compiler for Heterogeneous SoCs
  ☆26Updated 2 weeks ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆100Updated last year
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆121Updated this week
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆113Updated 3 months ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆28Updated 4 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆78Updated this week
• StanfordAHA / aha
  ☆54Updated this week
• pulp-platform / redmule
  ☆47Updated this week
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆142Updated 2 years ago