Alternatives and similar repositories for arc-tests

Users that are interested in arc-tests are comparing it to the libraries listed below

• iscas-tis / CHA
  ☆19Updated last year
• euphoric-hardware / rtl-simulation-reading
  ☆17Updated 2 months ago
• pku-liang / ksim
  ☆46Updated 7 months ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆54Updated this week
• iscas-tis / ChiRVFormal
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆14Updated 3 months ago
• sequencer / arithmetic
  ☆33Updated 5 months ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated last week
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆45Updated 2 months ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆37Updated 4 months ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 3 months ago
• iscas-tis / chisel-formal-verification
  Formal verification tools for Chisel and RISC-V
  ☆13Updated last year
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆29Updated 7 months ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆50Updated 2 years ago
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆52Updated 5 years ago
• euphoric-hardware / simcommand
  SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.
  ☆14Updated 2 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆35Updated 4 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 9 months ago
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆21Updated this week
• pku-liang / Hestia
  ☆17Updated 5 months ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆48Updated this week
• abs-tudelft / Tydi-Chisel
  ☆18Updated 5 months ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆21Updated 5 months ago
• chipsalliance / espresso
  ☆40Updated 3 months ago
• TsaiAnson / verif
  ☆12Updated 4 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆33Updated last year
• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 3 years ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago