circt / arc-tests
A collection of tests and benchmarks for the Arc simulation backend of CIRCT
☆28Updated 2 months ago
Alternatives and similar repositories for arc-tests:
Users that are interested in arc-tests are comparing it to the libraries listed below
- ☆40Updated 3 months ago
- ☆17Updated 3 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆27Updated 3 months ago
- ☆33Updated last month
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated last year
- A Modular Open-Source Hardware Fuzzing Framework☆32Updated 3 years ago
- A hardware synthesis framework with multi-level paradigm☆38Updated 3 months ago
- ☆18Updated 9 months ago
- Fast Symbolic Repair of Hardware Design Code☆22Updated 3 months ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆16Updated last month
- Equivalence checking with Yosys☆42Updated last week
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆13Updated this week
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- A Rocket-based RISC-V superscalar in-order core☆31Updated last week
- ☆13Updated 3 weeks ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- ☆38Updated last year
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆20Updated 3 months ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆19Updated last year
- Testing processors with Random Instruction Generation☆37Updated 2 weeks ago
- The 'missing header' for Chisel☆19Updated last month
- ☆11Updated 3 years ago
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆14Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆18Updated this week
- ILA Model Database☆22Updated 4 years ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆32Updated this week
- A fault-injection framework using Chisel and FIRRTL☆35Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- A Hardware Pipeline Description Language☆43Updated last year