ucb-bar / RoSELinks
A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robotic system.
☆43Updated 2 months ago
Alternatives and similar repositories for RoSE
Users that are interested in RoSE are comparing it to the libraries listed below
Sorting:
- ☆31Updated 2 months ago
- ☆59Updated this week
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- ☆60Updated last month
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 4 months ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆33Updated 2 weeks ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆28Updated 9 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆72Updated 6 years ago
- ☆30Updated 7 months ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- ☆25Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 8 months ago
- CGRA framework with vectorization support.☆32Updated last week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ☆11Updated last month
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆59Updated 2 weeks ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆47Updated 3 months ago
- ☆55Updated 3 months ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆92Updated 9 months ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- DASS HLS Compiler☆29Updated last year
- ☆71Updated 2 years ago
- ☆27Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago