A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robotic system.
☆46Apr 9, 2025Updated 11 months ago
Alternatives and similar repositories for RoSE
Users that are interested in RoSE are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆15Dec 9, 2025Updated 3 months ago
- ☆34Nov 6, 2024Updated last year
- An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics☆15Updated this week
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆14Aug 30, 2023Updated 2 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆50Jan 20, 2026Updated 2 months ago
- ☆16Jan 25, 2026Updated 2 months ago
- Analyze experimental data with Programming by Navigation☆17Mar 8, 2026Updated 2 weeks ago
- ☆19Jan 2, 2026Updated 2 months ago
- 21st century electronic design automation tools, written in Rust.☆36Mar 17, 2026Updated last week
- ☆28Feb 26, 2023Updated 3 years ago
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆20Oct 22, 2025Updated 5 months ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Nov 27, 2022Updated 3 years ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆54Mar 24, 2024Updated 2 years ago
- Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.☆45Sep 1, 2025Updated 6 months ago
- SKY130 SRAM macros generated by SRAM 22☆19Aug 19, 2025Updated 7 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆22Apr 25, 2025Updated 10 months ago
- Chisel RISC-V Vector 1.0 Implementation☆138Mar 18, 2026Updated last week
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆22Oct 31, 2024Updated last year
- Domain-Specific Architecture Generator 2☆22Oct 2, 2022Updated 3 years ago
- A Heterogeneous GPU Platform for Chipyard SoC☆47Updated this week
- Papers, Posters, Presentations, Documentation...☆19Jan 9, 2024Updated 2 years ago
- Quick & Flexible Rack-Scale Computer Architecture Simulator☆53Updated this week
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Oct 1, 2022Updated 3 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆314Mar 6, 2026Updated 2 weeks ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last month
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆17May 30, 2016Updated 9 years ago
- A configurable SRAM generator☆58Mar 4, 2026Updated 2 weeks ago
- A simulation framework for modeling efficiency of Graph Neural Network Dataflows☆23Feb 14, 2025Updated last year
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆36Jan 16, 2025Updated last year
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆25Nov 26, 2025Updated 3 months ago
- ☆15Apr 3, 2020Updated 5 years ago
- NeuraChip Accelerator Simulator☆16Apr 26, 2024Updated last year
- Release of stream-specialization software/hardware stack.☆122May 5, 2023Updated 2 years ago
- Graphical intuition to MOSFET square-law☆12Jan 5, 2021Updated 5 years ago
- The wafer-native AI accelerator simulation platform and inference engine.☆52Jan 1, 2026Updated 2 months ago
- ☆14Feb 28, 2023Updated 3 years ago
- RTLCheck☆25Oct 9, 2018Updated 7 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago