ucb-bar / RoSELinks
A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robotic system.
☆45Updated 9 months ago
Alternatives and similar repositories for RoSE
Users that are interested in RoSE are comparing it to the libraries listed below
Sorting:
- ☆62Updated this week
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆46Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆53Updated 2 years ago
- ☆32Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Updated 3 weeks ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 10 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 6 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆71Updated 5 months ago
- CGRA framework with vectorization support.☆42Updated last week
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 4 years ago
- Next generation CGRA generator☆118Updated last week
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆61Updated 6 months ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- ☆41Updated 9 months ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 6 years ago
- ☆22Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- ☆65Updated 8 months ago
- ☆36Updated 4 years ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆19Updated last year
- ☆17Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆90Updated 2 weeks ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆47Updated 6 months ago
- ☆61Updated 9 months ago