riscv-admin / integrated-matrix-extensionLinks
Administrative repository for the Integrated Matrix Extension Task Group
☆30Updated last week
Alternatives and similar repositories for integrated-matrix-extension
Users that are interested in integrated-matrix-extension are comparing it to the libraries listed below
Sorting:
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆47Updated this week
- ☆20Updated last month
- matrix-coprocessor for RISC-V☆25Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated 2 weeks ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆39Updated last month
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated this week
- Advanced Architecture Labs with CVA6☆71Updated last year
- HLS for Networks-on-Chip☆38Updated 4 years ago
- Development of a Network on Chip Simulation using SystemC.☆33Updated 8 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆127Updated last week
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆19Updated 10 months ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- Unit tests generator for RVV 1.0☆98Updated last month
- ☆89Updated last week
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆71Updated 3 weeks ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆13Updated last month
- Chisel RISC-V Vector 1.0 Implementation☆123Updated 2 months ago
- Public release☆58Updated 6 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆73Updated 5 years ago
- ☆70Updated 3 weeks ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Vector processor for RISC-V vector ISA☆131Updated 5 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆61Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆69Updated last year
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated 2 weeks ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆125Updated this week
- SystemVerilog Functional Coverage for RISC-V ISA☆32Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week