riscv-admin / integrated-matrix-extensionLinks
Administrative repository for the Integrated Matrix Extension Task Group
☆32Updated last month
Alternatives and similar repositories for integrated-matrix-extension
Users that are interested in integrated-matrix-extension are comparing it to the libraries listed below
Sorting:
- ☆21Updated 2 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆48Updated last month
- This is the fork of CVA6 intended for PULP development.☆21Updated last month
- matrix-coprocessor for RISC-V☆29Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- HLS for Networks-on-Chip☆39Updated 4 years ago
- Advanced Architecture Labs with CVA6☆73Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated last month
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆19Updated 2 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- ☆90Updated 3 weeks ago
- ☆33Updated last month
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 5 years ago
- Public release☆58Updated 6 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated 2 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆135Updated this week
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Updated this week
- ☆113Updated 2 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆33Updated last month
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆19Updated last week
- ☆57Updated 6 years ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆78Updated last month
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- ☆29Updated last year