riscv-admin / integrated-matrix-extensionLinks
Administrative repository for the Integrated Matrix Extension Task Group
☆25Updated last month
Alternatives and similar repositories for integrated-matrix-extension
Users that are interested in integrated-matrix-extension are comparing it to the libraries listed below
Sorting:
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆30Updated last year
- ☆15Updated 2 weeks ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆29Updated 9 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆85Updated this week
- matrix-coprocessor for RISC-V☆19Updated 2 months ago
- ☆51Updated 6 years ago
- ☆66Updated this week
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 3 weeks ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated this week
- Development of a Network on Chip Simulation using SystemC.☆33Updated 7 years ago
- Unit tests generator for RVV 1.0☆88Updated last month
- ☆26Updated last year
- Advanced Architecture Labs with CVA6☆62Updated last year
- HLS for Networks-on-Chip☆35Updated 4 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆11Updated 7 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆49Updated 8 months ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆11Updated last month
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- This is the fork of CVA6 intended for PULP development.☆21Updated 2 weeks ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- RISC-V Matrix Specification☆22Updated 6 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated this week
- Original test vector of RISC-V Vector Extension☆12Updated 4 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆11Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- General Purpose AXI Direct Memory Access☆51Updated last year