Alternatives and similar repositories for virgo:

Users that are interested in virgo are comparing it to the libraries listed below

• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆39Updated last week
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆38Updated last year
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated last year
• pku-liang / ksim
  ☆40Updated 2 months ago
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• CMU-SAFARI / VAMPIRE
  An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …
  ☆38Updated 6 years ago
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆25Updated 2 months ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆121Updated last year
• sequencer / arithmetic
  ☆32Updated last week
• ramisheikh / cbp2025
  Championship Branch Prediction 2025
  ☆33Updated last week
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆31Updated last year
• PrincetonUniversity / maple
  MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeli…
  ☆21Updated last year
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆73Updated 5 years ago
• CMU-SAFARI / GPGPUSim-Ramulator
  The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…
  ☆51Updated 5 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆70Updated 5 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆72Updated 6 months ago
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 3 years ago
• StanfordAHA / aha
  ☆55Updated this week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆88Updated last month
• zslwyuan / Light-HLS
  Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)
  ☆60Updated 3 years ago
• CMU-SAFARI / Load-Inspector
  A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…
  ☆20Updated 8 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆68Updated this week
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆51Updated 3 years ago
• suchandler96 / gem5-NVDLA
  ☆29Updated 6 months ago
• esa-tu-darmstadt / SCAIE-V
  An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
  ☆14Updated last year
• ucb-bar / RoSE
  A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…
  ☆41Updated last month
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆62Updated 8 months ago
• cdsc-github / parade-ara-simulator
  PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration
  ☆48Updated 2 years ago