ucb-bar / virgoLinks
Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
☆43Updated 5 months ago
Alternatives and similar repositories for virgo
Users that are interested in virgo are comparing it to the libraries listed below
Sorting:
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆34Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆67Updated 3 months ago
- ☆50Updated 10 months ago
- RISC-V Matrix Specification☆23Updated last year
- ☆106Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆59Updated 3 years ago
- A Heterogeneous GPU Platform for Chipyard SoC☆39Updated last week
- ☆39Updated 8 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆30Updated 2 weeks ago
- Chisel RISC-V Vector 1.0 Implementation☆121Updated last month
- ☆32Updated last year
- A DSL for Systolic Arrays☆82Updated 6 years ago
- gem5 FS模式实验手册☆44Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆44Updated 11 months ago
- upstream: https://github.com/RALC88/gem5☆33Updated 2 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆27Updated 11 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆71Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆72Updated last year
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆24Updated last week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆80Updated this week
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 5 months ago
- ☆11Updated last year
- Release of stream-specialization software/hardware stack.☆119Updated 2 years ago
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago