A submodule of Chipyard https://github.com/ucb-bar/chipyard
☆21Nov 4, 2026Updated this week
Alternatives and similar repositories for Baremetal-IDE
Users that are interested in Baremetal-IDE are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆15Sep 30, 2026Updated last month
- Configurable low-precision floating-point and microscaling hardware in Chisel☆13Oct 22, 2026Updated 2 weeks ago
- Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.☆49Oct 12, 2026Updated 3 weeks ago
- Chisel RISC-V Vector 1.0 Implementation☆159Updated this week
- ☆18Mar 11, 2026Updated 7 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- A Heterogeneous GPU Platform for AI and Neural Graphics☆72Updated this week
- A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…☆49Updated this week
- A configurable SRAM generator☆73Oct 20, 2026Updated 2 weeks ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆66Jun 27, 2025Updated last year
- A simple version of the MAX Object Detector Web App rewritten in python for use in the MAX tutorial☆10Mar 31, 2021Updated 5 years ago
- PCB libraries and templates for rocket-chip based FPGA/ASIC designs☆21Oct 28, 2026Updated last week
- ☆20Oct 2, 2026Updated last month
- A Rocket-based RISC-V superscalar in-order core☆42Updated this week
- A Single-path Delay Feedback FFT Generator☆15Mar 20, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆17Aug 26, 2025Updated last year
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆93Oct 15, 2026Updated 3 weeks ago
- Graphical intuition to MOSFET square-law☆12Jan 5, 2021Updated 5 years ago
- MLIR-in as a compiler stack for ucb-bar☆22Updated this week
- Bluetooth Low Energy Baseband☆15Dec 5, 2018Updated 7 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆26Sep 26, 2024Updated 2 years ago
- ☆17Sep 15, 2023Updated 3 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆329Aug 7, 2026Updated 2 months ago
- A programming language for writing constraint-based integrated circuit layout generators☆17Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 21st century electronic design automation tools, written in Rust.☆37Oct 13, 2026Updated 3 weeks ago
- Usage stats for the Berkeley EECS instructional computers.☆10Nov 21, 2024Updated last year
- ☆14Aug 31, 2025Updated last year
- Flexible Javascript timers which can be paused and modified on-the-fly☆13Mar 24, 2016Updated 10 years ago
- A Chisel RTL generator for network-on-chip interconnects☆240Nov 7, 2025Updated 11 months ago
- Workload ISA-Independent Characterization of Applications☆12Feb 2, 2017Updated 9 years ago
- ☆14Mar 20, 2025Updated last year
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 10 years ago
- chipyard in mill :P☆77Nov 20, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated 2 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆179May 26, 2025Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,448Updated this week
- ☆14Nov 12, 2023Updated 2 years ago
- Systemverilog and UVM exercises inspired by ziglings☆37Oct 26, 2026Updated last week
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆88Aug 28, 2023Updated 3 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆28Jan 11, 2019Updated 7 years ago