ByeBeihai / PolarisLinks
RISC-V SIMD Superscalar Dual-Issue Processor
☆24Updated 2 months ago
Alternatives and similar repositories for Polaris
Users that are interested in Polaris are comparing it to the libraries listed below
Sorting:
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- ☆47Updated 2 months ago
- The official NaplesPU hardware code repository☆17Updated 5 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated last month
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 months ago
- ☆22Updated 2 years ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆24Updated 3 weeks ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- Advanced Architecture Labs with CVA6☆65Updated last year
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆34Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆18Updated 2 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆38Updated 3 weeks ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆19Updated 2 months ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆32Updated 5 years ago
- ☆68Updated this week
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- ☆51Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 9 months ago
- cycle accurate Network-on-Chip Simulator☆28Updated 2 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated 11 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- matrix-coprocessor for RISC-V☆19Updated 2 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- DUTH RISC-V Microprocessor☆20Updated 7 months ago
- RISC-V Matrix Specification☆22Updated 7 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- ☆30Updated last week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago