RISC-V SIMD Superscalar Dual-Issue Processor
☆28Apr 24, 2025Updated 10 months ago
Alternatives and similar repositories for Polaris
Users that are interested in Polaris are comparing it to the libraries listed below
Sorting:
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Updated this week
- Formal Verification of RISC V IM Processor☆10Mar 27, 2022Updated 3 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated 2 weeks ago
- RV64GC Linux Capable RISC-V Core☆54Oct 20, 2025Updated 4 months ago
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- ☆21Feb 20, 2026Updated 2 weeks ago
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- An Open Source Link Protocol and Controller☆28Aug 1, 2021Updated 4 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- ☆13Jul 28, 2022Updated 3 years ago
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated last year
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Jan 19, 2026Updated last month
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆37Updated this week
- ☆18May 13, 2025Updated 9 months ago
- ☆17Dec 21, 2020Updated 5 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- 自建 chisel 工程模板☆14Jul 19, 2023Updated 2 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆22Mar 25, 2025Updated 11 months ago
- ☆10Dec 15, 2023Updated 2 years ago
- ☆35Jun 9, 2022Updated 3 years ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- ☆21Sep 26, 2025Updated 5 months ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆32Aug 22, 2024Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆49Jan 20, 2026Updated last month
- RISC-V vector extension ISA simulation☆16Jun 11, 2019Updated 6 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- ☆19Oct 7, 2025Updated 5 months ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Feb 27, 2025Updated last year
- ☆20Feb 19, 2026Updated 2 weeks ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆17Oct 5, 2023Updated 2 years ago
- Chisel RISC-V Vector 1.0 Implementation☆136Feb 25, 2026Updated last week
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆16Jun 24, 2020Updated 5 years ago
- Scalable Interface for RISC-V ISA Extensions☆23Mar 1, 2026Updated last week
- ☆78Feb 2, 2026Updated last month