ByeBeihai / Polaris
RISC-V SIMD Superscalar Dual-Issue Processor
☆11Updated last week
Alternatives and similar repositories for Polaris:
Users that are interested in Polaris are comparing it to the libraries listed below
- ☆9Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆18Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆47Updated 3 years ago
- ☆37Updated 2 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- ☆25Updated 4 years ago
- ☆12Updated 2 years ago
- ☆16Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- ☆26Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated this week
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆18Updated 3 months ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆9Updated last year
- CNN accelerator using NoC architecture☆15Updated 6 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- Design and UVM-TB of RISC -V Microprocessor☆14Updated 6 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆57Updated last year
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆21Updated 2 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- ☆13Updated last year
- DMA core compatible with AHB3-Lite☆10Updated 5 years ago
- Open IP in Hardware Description Language.☆18Updated last year
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆27Updated 4 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆22Updated last year
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 months ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- DMA controller for CNN accelerator☆13Updated 7 years ago
- eyeriss-chisel3☆40Updated 2 years ago