inferablejump / bagpypeLinks
☆15Updated 3 months ago
Alternatives and similar repositories for bagpype
Users that are interested in bagpype are comparing it to the libraries listed below
Sorting:
- ☆18Updated 2 months ago
- ☆12Updated 4 years ago
- 21st century electronic design automation tools, written in Rust.☆33Updated last week
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆32Updated 3 months ago
- Equivalence checking with Yosys☆51Updated 2 weeks ago
- A configurable SRAM generator☆57Updated 3 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- The 'missing header' for Chisel☆21Updated 8 months ago
- BFM Tester for Chisel HDL☆14Updated 4 years ago
- ☆41Updated 5 months ago
- A Heterogeneous GPU Platform for Chipyard SoC☆39Updated this week
- Intel Compiler for SystemC☆26Updated 2 years ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆48Updated 11 months ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆31Updated 4 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆29Updated this week
- For contributions of Chisel IP to the chisel community.☆68Updated last year
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- CMake based hardware build system☆32Updated 2 weeks ago
- A SystemVerilog language server based on the Slang library.☆68Updated this week
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated this week
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- design and verification of asynchronous circuits☆41Updated 2 weeks ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Updated 6 years ago
- Hardware generator debugger☆77Updated last year
- A stream to RTL compiler based on MLIR and CIRCT☆15Updated 3 years ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 5 months ago
- ☆33Updated 8 months ago
- ☆38Updated 3 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago