SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.
☆14Aug 30, 2023Updated 2 years ago
Alternatives and similar repositories for simcommand
Users that are interested in simcommand are comparing it to the libraries listed below
Sorting:
- compiling DSLs to high-level hardware instructions☆23Nov 8, 2022Updated 3 years ago
- A fork of Yosys that integrates the CellIFT pass☆13Jul 23, 2025Updated 7 months ago
- Hardware generator debugger☆77Feb 12, 2024Updated 2 years ago
- ☆12May 20, 2021Updated 4 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 2 years ago
- SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints☆31Sep 20, 2019Updated 6 years ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- ☆20Jun 12, 2024Updated last year
- A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…☆45Apr 9, 2025Updated 10 months ago
- Egraphs Modulo Theories☆18Jun 10, 2025Updated 8 months ago
- Papers, Posters, Presentations, Documentation...☆19Jan 9, 2024Updated 2 years ago
- A configurable SRAM generator☆58Aug 19, 2025Updated 6 months ago
- A Hardware Pipeline Description Language☆57Jul 12, 2025Updated 7 months ago
- DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language☆93Feb 17, 2026Updated last week
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆57Oct 27, 2024Updated last year
- Fast Symbolic Repair of Hardware Design Code☆33Jan 20, 2025Updated last year
- A Heterogeneous GPU Platform for Chipyard SoC☆43Updated this week
- The home of the Chisel3 website☆21May 24, 2024Updated last year
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆120Nov 10, 2025Updated 3 months ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- Chisel RISC-V Vector 1.0 Implementation☆133Updated this week
- (System)Verilog to Chisel translator☆116May 20, 2022Updated 3 years ago
- 🔁 elastic circuit toolchain☆32Dec 2, 2024Updated last year
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆36Jan 16, 2025Updated last year
- ☆35Jan 23, 2026Updated last month
- For contributions of Chisel IP to the chisel community.☆71Nov 7, 2024Updated last year
- design and verification of asynchronous circuits☆43Jan 18, 2026Updated last month
- Automatically generate a compiler using equality saturation☆34Apr 3, 2024Updated last year
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆313Feb 20, 2026Updated last week
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 5 months ago
- High level synthesis language for hardware design☆80Updated this week
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆41Jul 17, 2024Updated last year
- A framework for formally verifying hardware security modules to be free of hardware, software, and timing side-channel vulnerabilities 🔏☆40Nov 29, 2025Updated 2 months ago
- 21st century electronic design automation tools, written in Rust.☆36Feb 20, 2026Updated last week
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- End-to-end synthesis and P&R toolchain☆94Feb 20, 2026Updated last week
- A core language for rule-based hardware design 🦑☆172Dec 10, 2025Updated 2 months ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago