riscv-admin / attached-matrix-extension
Administrative repository for the Attached Matrix Facility Task Group
☆10Updated last year
Alternatives and similar repositories for attached-matrix-extension:
Users that are interested in attached-matrix-extension are comparing it to the libraries listed below
- Administrative repository for the Integrated Matrix Extension Task Group☆18Updated 6 months ago
- RISC-V Matrix Specification☆19Updated 3 months ago
- RiVEC Bencmark Suite☆113Updated 4 months ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆11Updated 2 years ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆28Updated last year
- Unit tests generator for RVV 1.0☆79Updated last week
- A matrix extension proposal for AI applications under RISC-V architecture☆133Updated last month
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆43Updated 4 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆20Updated 3 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆64Updated this week
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆69Updated 5 years ago
- Release of stream-specialization software/hardware stack.☆121Updated last year
- ☆43Updated 5 years ago
- ☆91Updated last year
- A scalable High-Level Synthesis framework on MLIR☆252Updated 10 months ago
- An Open-Source Tool for CGRA Accelerators☆59Updated 2 months ago
- Following the RISC-V IME extension standard, and reusing Vector register resources, these instructions can bring more than a tenfold perf…☆54Updated 7 months ago
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆108Updated this week
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆55Updated last month
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆145Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆58Updated 5 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- Source Code for training and evaluating BranchNet models for branch prediction☆33Updated 4 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 8 months ago
- Ventus GPGPU ISA Simulator Based on Spike☆42Updated last month
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago