Administrative repository for the Attached Matrix Facility Task Group
☆14Dec 11, 2023Updated 2 years ago
Alternatives and similar repositories for attached-matrix-extension
Users that are interested in attached-matrix-extension are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Administrative repository for the Integrated Matrix Extension Task Group☆36Apr 25, 2026Updated last month
- RISC-V Matrix Specification☆26Dec 2, 2024Updated last year
- Scalable Interface for RISC-V ISA Extensions☆26Updated this week
- LibOCXL is an access library which allows the user to implement a userspace driver for an OpenCAPI accelerator.☆13Jul 1, 2024Updated last year
- A hand-written recursive decent Verilog parser.☆10May 7, 2026Updated last month
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This repo hold information on the open-standard OVP APIs☆20Dec 11, 2025Updated 6 months ago
- SmartNIC☆14Dec 13, 2018Updated 7 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆183Apr 1, 2026Updated 2 months ago
- Python bindings for VE Offloading (VEO) for SX-Aurora Vector Engine☆17Dec 27, 2023Updated 2 years ago
- Module for LST retrieval from Landsat-8/TIRS imagery based on practical split-window algorithm + covariance-variance ratio (SWCVR) method☆11May 27, 2025Updated last year
- SoC for CQU Dual Issue Machine☆12Sep 20, 2022Updated 3 years ago
- MIPS 57条指令五级流水线cpu (verilog实现+详细注释)☆11Jan 11, 2022Updated 4 years ago
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆17Mar 26, 2026Updated 2 months ago
- ☆25Apr 12, 2026Updated 2 months ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- RISCV lock-step checker based on Spike☆14Mar 6, 2026Updated 3 months ago
- SystemVerilog file list pruner☆19Mar 2, 2026Updated 3 months ago
- Mirror of git://qemu.org/capstone.git☆10Updated this week
- VHDL code generator for AXI4-lite register files☆12May 22, 2024Updated 2 years ago
- Graphviz dot to Verilog Finite State Machine (FSM) generator written in Python☆15Feb 3, 2021Updated 5 years ago
- Filelist generator☆21Jun 9, 2026Updated last week
- ☆109May 15, 2026Updated last month
- Heterogeneous Active Messages C++ library☆21Nov 8, 2019Updated 6 years ago
- Debug waveforms with GDB☆33Nov 12, 2025Updated 7 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆18Nov 11, 2025Updated 7 months ago
- Implementation of a 32-bit single core risc-v platfrom for Xilinx zcu102 board☆13Nov 5, 2019Updated 6 years ago
- ☆26Jun 5, 2026Updated last week
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- Coverview☆32Jun 3, 2026Updated last week
- cocotb code library☆13Dec 28, 2020Updated 5 years ago
- Hardware transactions library for Amaranth☆27Jun 1, 2026Updated 2 weeks ago
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆31Feb 10, 2026Updated 4 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated 10 months ago
- 一个复刻Apple Newsroom的博客网站☆12Nov 7, 2024Updated last year
- ☆19May 20, 2026Updated 3 weeks ago
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆17Oct 4, 2022Updated 3 years ago
- ☆20Jan 2, 2026Updated 5 months ago
- Labs for the Ibex Demo System☆18Nov 18, 2023Updated 2 years ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆38Mar 26, 2024Updated 2 years ago