Alternatives and similar repositories for rocket-tools

Users that are interested in rocket-tools are comparing it to the libraries listed below

• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆174Updated last month
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆126Updated 4 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆106Updated last week
• riscv-ovpsim / imperas-riscv-tests
  ☆182Updated last year
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆65Updated 7 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 2 weeks ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆87Updated 3 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated last week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆101Updated 3 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆100Updated 2 months ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆121Updated 2 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆43Updated 2 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆126Updated 3 weeks ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• ucb-bar / uciedigital
  Pure digital components of a UCIe controller
  ☆67Updated last month
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆197Updated last year
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆154Updated 9 months ago
• ucb-bar / sha3
  ☆81Updated last year
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 5 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆90Updated last week
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆73Updated 2 months ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆65Updated 9 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆120Updated last month
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆83Updated last year