chipsalliance / rocket-toolsLinks
Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
☆59Updated 2 years ago
Alternatives and similar repositories for rocket-tools
Users that are interested in rocket-tools are comparing it to the libraries listed below
Sorting:
- Setup scripts and files needed to compile CoreMark on RISC-V☆72Updated last year
- Open source high performance IEEE-754 floating unit☆88Updated last year
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆192Updated 3 months ago
- Generic Register Interface (contains various adapters)☆134Updated last month
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Open-source high-performance non-blocking cache☆92Updated last month
- The multi-core cluster of a PULP system.☆111Updated last week
- ☆192Updated 2 years ago
- ☆99Updated 4 months ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆108Updated 3 months ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 10 months ago
- RISC-V Verification Interface☆136Updated last month
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Vector processor for RISC-V vector ISA☆134Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- An Open-Source Design and Verification Environment for RISC-V☆86Updated 4 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆76Updated last month
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- ☆82Updated last year
- PCI Express controller model☆71Updated 3 years ago
- Chisel Learning Journey☆111Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Verilog Configurable Cache☆190Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 6 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated 2 years ago
- A dynamic verification library for Chisel.☆159Updated last year