Alternatives and similar repositories for rocket-tools:

Users that are interested in rocket-tools are comparing it to the libraries listed below

• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆64Updated 6 months ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆64Updated 5 years ago
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆116Updated 3 weeks ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆61Updated 7 months ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆58Updated last year
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆84Updated this week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆60Updated 5 months ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆101Updated 2 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆128Updated 2 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆57Updated 2 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆144Updated 2 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last week
• ucb-bar / sha3
  ☆77Updated 11 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆167Updated last year
• riscv / riscv-aclint
  ☆42Updated 3 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆156Updated this week
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆69Updated 4 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆57Updated last year
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆112Updated 4 years ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆67Updated 11 months ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆35Updated 2 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆111Updated 2 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆64Updated this week
• riscv / riscv-CMOs
  ☆83Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆65Updated 9 months ago
• sequencer / arithmetic
  ☆32Updated this week
• chipsalliance / uvm-verilator
  ☆82Updated last year
• ucb-bar / testchipip
  ☆82Updated 2 weeks ago