Alternatives and similar repositories for rocket-tools

Users that are interested in rocket-tools are comparing it to the libraries listed below

• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆190Updated last year
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆85Updated last year
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 2 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆90Updated last month
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆108Updated this week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆184Updated last month
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆129Updated 5 years ago
• ucb-bar / sha3
  ☆80Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆74Updated last week
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆99Updated 2 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆110Updated 2 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆137Updated 3 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆122Updated 2 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆156Updated 11 months ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆96Updated 2 months ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆67Updated last month
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆84Updated 4 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆200Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated 3 weeks ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆67Updated last month
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 7 months ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆76Updated this week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆104Updated last month
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆184Updated 2 weeks ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆112Updated 2 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago