Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
☆62Oct 1, 2023Updated 2 years ago
Alternatives and similar repositories for rocket-tools
Users that are interested in rocket-tools are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Wrapper for Rocket-Chip on FPGAs☆139Oct 5, 2022Updated 3 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- This is my first trial project for designing RISC-V in Chisel☆17Apr 29, 2024Updated 2 years ago
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated last year
- Rocket Chip Generator☆3,803Jun 2, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The home of the Chisel3 website☆21May 24, 2024Updated 2 years ago
- PCB libraries and templates for rocket-chip based FPGA/ASIC designs☆19Jun 4, 2026Updated 3 weeks ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆90Mar 17, 2026Updated 3 months ago
- A template project for beginning new Chisel work☆702Feb 24, 2026Updated 4 months ago
- Provides dot visualizations of chisel/firrtl circuits☆123Apr 14, 2023Updated 3 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆165Jan 25, 2024Updated 2 years ago
- chisel tutorial exercises and answers☆753Jan 6, 2022Updated 4 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆50Jan 12, 2023Updated 3 years ago
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,299Jun 22, 2026Updated last week
- Support for Rocket Chip on Zynq FPGAs☆422Jan 29, 2019Updated 7 years ago
- ☆92May 29, 2026Updated last month
- Jtag parsing scripts☆10Oct 14, 2023Updated 2 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 3 years ago
- Verilator open-source SystemVerilog simulator and lint system☆43Updated this week
- Run Rocket Chip on VCU128☆30Oct 21, 2025Updated 8 months ago
- SystemVerilog language server client for Visual Studio Code☆23Dec 30, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Chisel: A Modern Hardware Design Language☆4,701Updated this week
- CLI tool for RTL design space exploration on top of Vivado☆15Jun 5, 2023Updated 3 years ago
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 5 years ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆234Aug 19, 2024Updated last year
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,138Sep 10, 2024Updated last year
- SiFive OpenEmbedded / Yocto BSP Layer☆56Jun 25, 2026Updated last week
- ☆13Mar 13, 2026Updated 3 months ago
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- GateKeeper: Fast Alignment Filter for DNA Short Read Mapping☆22Mar 5, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Verilog AST☆21Dec 2, 2023Updated 2 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆20Apr 27, 2024Updated 2 years ago
- Freedom U Software Development Kit (FUSDK)☆302Jun 25, 2026Updated last week
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- Custom Coprocessor Interface for VexRiscv☆10Sep 19, 2018Updated 7 years ago
- ☆19Jun 25, 2026Updated last week
- Coverview☆32Jun 3, 2026Updated 3 weeks ago