chipsalliance / rocket-tools
Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
☆54Updated last year
Alternatives and similar repositories for rocket-tools:
Users that are interested in rocket-tools are comparing it to the libraries listed below
- Vector processor for RISC-V vector ISA☆117Updated 4 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 9 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆146Updated last week
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- Open source high performance IEEE-754 floating unit☆70Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 8 months ago
- RISC-V Verification Interface☆89Updated 2 months ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- A dynamic verification library for Chisel.☆148Updated 5 months ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- ☆92Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆91Updated last month
- Provides various testers for chisel users☆100Updated 2 years ago
- Wrapper for Rocket-Chip on FPGAs☆132Updated 2 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆65Updated 10 months ago
- An Open-Source Design and Verification Environment for RISC-V☆80Updated 4 years ago
- Generic Register Interface (contains various adapters)☆116Updated 7 months ago
- Chisel Learning Journey☆109Updated 2 years ago
- SystemVerilog modules and classes commonly used for verification☆47Updated 4 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated 2 weeks ago
- A Fast, Low-Overhead On-chip Network☆200Updated last week
- ☆42Updated 3 years ago
- Pure digital components of a UCIe controller☆62Updated last week
- Verilog Configurable Cache☆178Updated 5 months ago
- The multi-core cluster of a PULP system.☆90Updated last week
- Unit tests generator for RVV 1.0☆83Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆96Updated last month
- Network on Chip Implementation written in SytemVerilog☆174Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆53Updated 3 years ago