chipsalliance / rocket-toolsLinks
Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
☆59Updated 2 years ago
Alternatives and similar repositories for rocket-tools
Users that are interested in rocket-tools are comparing it to the libraries listed below
Sorting:
- Setup scripts and files needed to compile CoreMark on RISC-V☆71Updated last year
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Generic Register Interface (contains various adapters)☆133Updated last month
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- The multi-core cluster of a PULP system.☆109Updated 2 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆186Updated last month
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- Vector processor for RISC-V vector ISA☆130Updated 5 years ago
- Chisel Learning Journey☆110Updated 2 years ago
- Open-source high-performance non-blocking cache☆91Updated last week
- Open source high performance IEEE-754 floating unit☆86Updated last year
- ☆189Updated last year
- ☆96Updated 2 months ago
- CVA6 SDK containing RISC-V tools and Buildroot☆75Updated 3 weeks ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- RISC-V System on Chip Template☆159Updated 2 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆122Updated 4 months ago
- A dynamic verification library for Chisel.☆157Updated last year
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Provides various testers for chisel users☆100Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- RISC-V Verification Interface☆112Updated last week
- ☆89Updated 2 months ago
- ☆81Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆106Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- An Open-Source Design and Verification Environment for RISC-V☆85Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago