Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
☆62Oct 1, 2023Updated 3 years ago
Alternatives and similar repositories for rocket-tools
Users that are interested in rocket-tools are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- The home of the Chisel3 website☆21May 24, 2024Updated 2 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Rocket Chip Generator☆3,894Sep 13, 2026Updated last month
- A scala based simulator for circuits described by a LoFirrtl file☆51Jan 12, 2023Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Wrapper for Rocket-Chip on FPGAs☆142Oct 5, 2022Updated 4 years ago
- This is my first trial project for designing RISC-V in Chisel☆17Apr 29, 2024Updated 2 years ago
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated 2 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆93Oct 15, 2026Updated 2 weeks ago
- An FPGA-accelerated version of minimap2☆11May 30, 2023Updated 3 years ago
- A template project for beginning new Chisel work☆710Feb 24, 2026Updated 8 months ago
- Tools for SiFive's Freedom Platform☆218Aug 26, 2021Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuits☆123Apr 14, 2023Updated 3 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- chisel tutorial exercises and answers☆758Jan 6, 2022Updated 4 years ago
- Support for Rocket Chip on Zynq FPGAs☆425Jan 29, 2019Updated 7 years ago
- SiFive OpenEmbedded / Yocto BSP Layer☆58Updated this week
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated 2 years ago
- Jtag parsing scripts☆10Oct 14, 2023Updated 3 years ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆234Aug 19, 2024Updated 2 years ago
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 3 years ago
- PCB libraries and templates for rocket-chip based FPGA/ASIC designs☆19Oct 20, 2026Updated last week
- ☆92Oct 20, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,442Updated this week
- Chisel: A Modern Hardware Design Language☆4,827Updated this week
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 8 years ago
- Verilator open-source SystemVerilog simulator and lint system☆45Sep 29, 2026Updated last month
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆13Jan 26, 2026Updated 9 months ago
- Run Rocket Chip on VCU128☆30Oct 21, 2025Updated last year
- Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, …☆11Nov 23, 2023Updated 2 years ago
- educational microarchitectures for risc-v isa☆68Feb 18, 2019Updated 7 years ago
- Flute 3.1 with CMake support☆16Jul 25, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SystemVerilog language server client for Visual Studio Code☆23Dec 30, 2022Updated 3 years ago
- CLI tool for RTL design space exploration on top of Vivado☆15Jun 5, 2023Updated 3 years ago
- ☆14Apr 29, 2024Updated 2 years ago
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- Scripts for XiangShan☆18Updated this week
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- The specification for the FIRRTL language☆68Updated this week