Alternatives and similar repositories for vivado-risc-v

Users that are interested in vivado-risc-v are comparing it to the libraries listed below

• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,036Updated 3 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,080Updated 3 weeks ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,517Updated 8 months ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,281Updated 11 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,568Updated last week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,308Updated this week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆918Updated 7 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆885Updated 4 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆883Updated 2 years ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,476Updated 3 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,135Updated 2 weeks ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆842Updated last month
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,042Updated 9 months ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,742Updated 3 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆810Updated 3 years ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆730Updated 3 years ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,351Updated last year
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆715Updated 3 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆627Updated this week
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆475Updated 3 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆624Updated 3 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,872Updated this week
• KastnerRG / riffa
  The RIFFA development repository
  ☆835Updated last year
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,803Updated last week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆581Updated 10 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆556Updated 2 weeks ago
• alexforencich / verilog-uart
  Verilog UART
  ☆490Updated 3 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,300Updated last year
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,600Updated 2 weeks ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆710Updated last month