Alternatives and similar repositories for vivado-risc-v:

Users that are interested in vivado-risc-v are comparing it to the libraries listed below

• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆926Updated 3 years ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,001Updated 4 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆893Updated 2 months ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,337Updated 3 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,188Updated last week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,004Updated 6 months ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆800Updated this week
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆708Updated 3 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,453Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,057Updated 5 months ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,378Updated 3 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆856Updated 3 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆840Updated last year
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆611Updated this week
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,196Updated 7 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆726Updated 3 years ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆558Updated 5 months ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,194Updated 9 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆698Updated 5 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆560Updated 2 weeks ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆478Updated last week
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,594Updated last year
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,240Updated 8 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,730Updated this week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆467Updated 2 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆769Updated 5 months ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆396Updated 3 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆437Updated last year
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆402Updated 6 years ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,719Updated this week