eugene-tarassov / vivado-risc-v

Related projects ⓘ

Alternatives and complementary repositories for vivado-risc-v

• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆863Updated 3 years ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆976Updated last month
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆818Updated last year
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,095Updated this week
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,268Updated last month
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆959Updated 3 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,371Updated last month
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆860Updated last month
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆767Updated this week
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,255Updated 3 years ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,132Updated 6 months ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,499Updated 11 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆545Updated 3 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆836Updated 3 years ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,161Updated 4 months ago
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆584Updated 5 months ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆694Updated 2 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,017Updated 2 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆707Updated 3 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆543Updated 3 months ago
• riscv-software-src / riscv-tests
  ☆891Updated this week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,639Updated this week
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆738Updated 3 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆513Updated this week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆687Updated 2 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆620Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆557Updated 2 weeks ago
• riscv-non-isa / riscv-arch-test
  ☆514Updated this week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆451Updated 6 months ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,736Updated last month