Alternatives and similar repositories for riscv_vhdl:

Users that are interested in riscv_vhdl are comparing it to the libraries listed below

• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,028Updated last month
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆862Updated last year
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆269Updated 7 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆972Updated 3 years ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆904Updated 4 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,494Updated 3 weeks ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆669Updated 3 weeks ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆710Updated 2 weeks ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆523Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,080Updated last month
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,256Updated last week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆673Updated 2 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆590Updated last week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆317Updated 9 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆598Updated 2 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆526Updated last month
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,240Updated this week
• riscv-non-isa / riscv-arch-test
  ☆549Updated this week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆410Updated last week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆506Updated this week
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆620Updated 2 weeks ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆863Updated 4 years ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆478Updated last month
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆265Updated 4 years ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆760Updated 3 years ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,261Updated 10 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆867Updated 3 years ago
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆596Updated last year
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆407Updated 6 years ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,514Updated last week