Alternatives and similar repositories for riscv_vhdl

Users that are interested in riscv_vhdl are comparing it to the libraries listed below

• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,077Updated this week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆878Updated 2 years ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆914Updated 6 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,547Updated 2 weeks ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆274Updated 9 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆701Updated last month
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆535Updated 2 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆560Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆620Updated 3 weeks ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆630Updated last week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆714Updated 2 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,126Updated 3 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆545Updated last week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆602Updated 3 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆426Updated 2 weeks ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆325Updated 11 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,293Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,024Updated 3 years ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆866Updated 5 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,286Updated this week
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆636Updated 2 weeks ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆408Updated 6 years ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆493Updated 6 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆575Updated 2 weeks ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆706Updated last week
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆741Updated 9 months ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,589Updated 2 weeks ago
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆579Updated 4 years ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,289Updated last year
• riscv-non-isa / riscv-arch-test
  ☆564Updated 2 weeks ago