Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
☆684Jul 16, 2025Updated 7 months ago
Alternatives and similar repositories for riscv_vhdl
Users that are interested in riscv_vhdl are comparing it to the libraries listed below
Sorting:
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆417Feb 20, 2026Updated 2 weeks ago
- A simple RISC-V processor for use in FPGA designs.☆283Aug 19, 2024Updated last year
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆964Nov 15, 2024Updated last year
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,498Jan 7, 2026Updated 2 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,032Feb 11, 2026Updated 3 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,190May 26, 2025Updated 9 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,986Jun 27, 2024Updated last year
- Verilog library for ASIC and FPGA designers☆1,395May 8, 2024Updated last year
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆1,999Updated this week
- 32-bit Superscalar RISC-V CPU☆1,183Sep 18, 2021Updated 4 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,828Feb 25, 2026Updated last week
- SERV - The SErial RISC-V CPU☆1,761Feb 19, 2026Updated 2 weeks ago
- VHDL compiler and simulator☆780Updated this week
- Rocket Chip Generator☆3,705Feb 25, 2026Updated last week
- RISC-V CPU Core☆411Jun 24, 2025Updated 8 months ago
- The root repo for lowRISC project and FPGA demos.☆602Aug 3, 2023Updated 2 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆577Aug 21, 2025Updated 6 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- A Linux-capable RISC-V multicore for and by the world☆771Feb 9, 2026Updated 3 weeks ago
- educational microarchitectures for risc-v isa☆741Sep 1, 2025Updated 6 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆571Oct 21, 2025Updated 4 months ago
- A small, light weight, RISC CPU soft core☆1,514Dec 8, 2025Updated 3 months ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,083Feb 5, 2026Updated last month
- Hardware Description Languages☆1,116Jul 14, 2025Updated 7 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆649Jan 19, 2026Updated last month
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆601Jul 30, 2025Updated 7 months ago
- RISC-V Formal Verification Framework☆624Apr 6, 2022Updated 3 years ago
- Support for Rocket Chip on Zynq FPGAs☆417Jan 29, 2019Updated 7 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆659Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆336Dec 11, 2024Updated last year
- RISC-V CPU Core (RV32IM)☆1,656Sep 18, 2021Updated 4 years ago
- An open-source microcontroller system based on RISC-V☆1,010Feb 6, 2024Updated 2 years ago
- VHDL 2008/93/87 simulator☆2,767Updated this week
- Working Draft of the RISC-V Debug Specification Standard☆505Mar 1, 2026Updated last week
- The OpenPiton Platform☆774Feb 25, 2026Updated last week
- Common SystemVerilog components☆718Feb 26, 2026Updated last week
- A huge VHDL library for FPGA and digital ASIC development☆449Feb 23, 2026Updated last week
- VUnit is a unit testing framework for VHDL/SystemVerilog☆818Feb 26, 2026Updated last week