Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
☆688Jul 16, 2025Updated 11 months ago
Alternatives and similar repositories for riscv_vhdl
Users that are interested in riscv_vhdl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A simple RISC-V processor for use in FPGA designs.☆286Aug 19, 2024Updated last year
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆424Jun 9, 2026Updated last week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆982Nov 15, 2024Updated last year
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆2,143Updated this week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,570May 12, 2026Updated last month
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,166Feb 11, 2026Updated 4 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,217Jun 27, 2024Updated last year
- VHDL compiler and simulator☆839Updated this week
- 32-bit Superscalar RISC-V CPU☆1,259Sep 18, 2021Updated 4 years ago
- Verilog library for ASIC and FPGA designers☆1,421May 8, 2024Updated 2 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,247May 29, 2026Updated 2 weeks ago
- SERV - The SErial RISC-V CPU☆1,812Feb 19, 2026Updated 3 months ago
- Rocket Chip Generator☆3,795Jun 2, 2026Updated 2 weeks ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,969Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The root repo for lowRISC project and FPGA demos.☆600Aug 3, 2023Updated 2 years ago
- RISC-V CPU Core☆436Jun 24, 2025Updated 11 months ago
- mor1kx - an OpenRISC 1000 processor IP core☆585Jun 6, 2026Updated last week
- Support for Rocket Chip on Zynq FPGAs☆422Jan 29, 2019Updated 7 years ago
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆606Jul 30, 2025Updated 10 months ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆223Jan 23, 2020Updated 6 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,181Mar 11, 2026Updated 3 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆614May 26, 2026Updated 3 weeks ago
- Hardware Description Languages☆1,153Apr 6, 2026Updated 2 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- educational microarchitectures for risc-v isa☆748Sep 1, 2025Updated 9 months ago
- A small, light weight, RISC CPU soft core☆1,552Dec 8, 2025Updated 6 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆242Nov 20, 2024Updated last year
- Learn and build GPU RTL from scratch☆21Aug 1, 2025Updated 10 months ago
- A Linux-capable RISC-V multicore for and by the world☆812Jun 5, 2026Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆669May 11, 2026Updated last month
- VHDL 2008/93/87 simulator☆2,834Updated this week
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆71Feb 13, 2025Updated last year
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆448Apr 22, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A huge VHDL library for FPGA and digital ASIC development☆465Updated this week
- Basic RISC-V CPU implementation in VHDL.☆177Sep 13, 2020Updated 5 years ago
- An open-source microcontroller system based on RISC-V☆1,040Feb 6, 2024Updated 2 years ago
- Generic Register Interface (contains various adapters)☆140May 15, 2026Updated last month
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆379Jul 12, 2017Updated 8 years ago
- A 32-bit RISC-V soft processor☆328Jan 26, 2026Updated 4 months ago
- RISC-V SystemC-TLM simulator☆353Feb 20, 2026Updated 3 months ago