li3tuo4 / rc-fpga-zcu
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
☆61Updated 2 years ago
Alternatives and similar repositories for rc-fpga-zcu
Users that are interested in rc-fpga-zcu are comparing it to the libraries listed below
Sorting:
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 9 months ago
- ☆81Updated last year
- CVA6 SDK containing RISC-V tools and Buildroot☆65Updated 10 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆72Updated 3 weeks ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- Wrapper for Rocket-Chip on FPGAs☆133Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆52Updated 5 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆54Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆53Updated 3 years ago
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆133Updated last year
- ☆56Updated 4 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Chisel Learning Journey☆109Updated 2 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- ☆86Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆30Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆91Updated last month
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆51Updated 4 years ago
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆35Updated 5 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- Run rocket-chip on FPGA☆67Updated 6 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆151Updated this week