eliaskousk / parallella-riscvLinks
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
☆106Updated 7 years ago
Alternatives and similar repositories for parallella-riscv
Users that are interested in parallella-riscv are comparing it to the libraries listed below
Sorting:
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 6 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆175Updated 5 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- Connectal is a framework for software-driven hardware development.☆176Updated 2 years ago
- A Tiny Processor Core☆114Updated 5 months ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 5 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- OmniXtend cache coherence protocol☆82Updated 7 months ago
- A utility for Composing FPGA designs from Peripherals☆186Updated last year
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago
- RISC-V Virtual Prototype☆183Updated last year
- FuseSoC standard core library☆151Updated last month
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 7 months ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 8 months ago
- Chisel components for FPGA projects☆128Updated 2 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- ☆99Updated 4 months ago
- Altera Advanced Synthesis Cookbook 11.0☆112Updated 2 years ago
- Labs to learn SpinalHDL☆151Updated last year
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆219Updated 5 years ago
- ☆88Updated 3 years ago