eliaskousk / parallella-riscv
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
☆98Updated 5 years ago
Related projects: ⓘ
- Parallel Array of Simple Cores. Multicore processor.☆92Updated 5 years ago
- Yet Another RISC-V Implementation☆82Updated 8 months ago
- Riscy Processors - Open-Sourced RISC-V Processors☆72Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆80Updated 3 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆77Updated 4 years ago
- Basic floating-point components for RISC-V processors☆62Updated 4 years ago
- educational microarchitectures for risc-v isa☆64Updated 5 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆119Updated 5 years ago
- Documentation for the BOOM processor☆47Updated 7 years ago
- Connectal is a framework for software-driven hardware development.☆161Updated 11 months ago
- FPGA reference design for the the Swerv EH1 Core☆65Updated 4 years ago
- ☆63Updated 5 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆54Updated 7 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆59Updated 2 months ago
- Ethernet MAC 10/100 Mbps☆75Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆44Updated 4 years ago
- ☆44Updated 3 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆61Updated 2 months ago
- ☆72Updated 8 months ago
- Support for Rocket Chip on Zynq FPGAs☆39Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆53Updated 4 years ago
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- ☆132Updated 2 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆86Updated 3 years ago
- FuseSoC standard core library☆105Updated last month
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆196Updated 4 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆145Updated 6 years ago
- OmniXtend cache coherence protocol☆76Updated 4 years ago
- A simple RISC-V core, described with Verilog☆26Updated 11 years ago
- Common RTL blocks used in SiFive's projects☆177Updated 2 years ago