Alternatives and similar repositories for DiplomaticBackend

Users that are interested in DiplomaticBackend are comparing it to the libraries listed below

• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆24Updated last week
• pku-liang / ksim
  ☆52Updated last year
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆24Updated 8 months ago
• sequencer / arithmetic
  ☆33Updated 10 months ago
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• openhwgroup / cv-hpdcache-verif
  Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
  ☆19Updated 2 weeks ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆35Updated 2 weeks ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆32Updated this week
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• chipsalliance / espresso
  ☆41Updated last month
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆51Updated 5 years ago
• OpenXiangShan / gsim
  ☆64Updated 3 weeks ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆97Updated last week
• kuczmmar / Runahead
  Running ahead of memory latency - Part II project
  ☆10Updated 3 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last month
• OpenXiangShan / tl-test-new
  The Unified TileLink Memory Subsystem Tester for XiangShan
  ☆12Updated 2 weeks ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆13Updated 4 years ago
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆13Updated 2 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 3 months ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆111Updated 2 years ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆33Updated 2 years ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆15Updated 3 years ago
• iscas-tis / chisel-formal-verification
  Formal verification tools for Chisel and RISC-V
  ☆13Updated last year
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• ucb-bar / radiance
  A Heterogeneous GPU Platform for Chipyard SoC
  ☆41Updated last week
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 4 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆52Updated this week
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆33Updated last year
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆76Updated last week