davidepatti / noximLinks
Network on Chip Simulator
☆285Updated 3 weeks ago
Alternatives and similar repositories for noxim
Users that are interested in noxim are comparing it to the libraries listed below
Sorting:
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆296Updated 2 months ago
- ☆182Updated last month
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆451Updated last week
- A Chisel RTL generator for network-on-chip interconnects☆207Updated 3 months ago
- BookSim 2.0☆347Updated last year
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆276Updated 3 months ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆127Updated 7 years ago
- An AXI4 crossbar implementation in SystemVerilog☆166Updated last month
- RISC-V SystemC-TLM simulator☆314Updated 7 months ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆381Updated 3 weeks ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆239Updated 2 years ago
- A Fast, Low-Overhead On-chip Network☆220Updated last week
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆388Updated last year
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆190Updated 5 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆135Updated last month
- Network on Chip Implementation written in SytemVerilog☆186Updated 2 years ago
- SystemC/TLM-2.0 Co-simulation framework☆252Updated 2 months ago
- Collect some IC textbooks for learning.☆151Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆173Updated 8 months ago
- IC implementation of Systolic Array for TPU☆263Updated 9 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆198Updated 5 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆155Updated 2 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆181Updated 5 years ago
- IC implementation of TPU☆128Updated 5 years ago
- ☆334Updated 10 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated last week
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆138Updated last year
- An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model☆478Updated last year