davidepatti / noximLinks
Network on Chip Simulator
☆297Updated 2 months ago
Alternatives and similar repositories for noxim
Users that are interested in noxim are comparing it to the libraries listed below
Sorting:
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆325Updated 2 weeks ago
- A Chisel RTL generator for network-on-chip interconnects☆223Updated last month
- ☆214Updated 6 months ago
- BookSim 2.0☆388Updated last year
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆288Updated 2 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆481Updated last month
- An AXI4 crossbar implementation in SystemVerilog☆198Updated 3 months ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆254Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆257Updated 2 weeks ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆208Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆140Updated 7 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆398Updated 2 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆165Updated 2 years ago
- Network on Chip Implementation written in SytemVerilog☆196Updated 3 years ago
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆434Updated last year
- GPGPU supporting RISCV-V, developed with verilog HDL☆134Updated 10 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆149Updated this week
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆205Updated 5 years ago
- RISC-V SystemC-TLM simulator☆335Updated last month
- ☆362Updated 3 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆185Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆177Updated 6 years ago
- Collect some IC textbooks for learning.☆179Updated 3 years ago
- SystemC/TLM-2.0 Co-simulation framework☆263Updated 7 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆112Updated 5 years ago
- Modeling Architectural Platform☆214Updated last week
- Vector processor for RISC-V vector ISA☆133Updated 5 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆275Updated 3 weeks ago
- PandA-bambu public repository☆302Updated last week
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆217Updated last month