matutani / nocgen
NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
☆60Updated 5 years ago
Alternatives and similar repositories for nocgen:
Users that are interested in nocgen are comparing it to the libraries listed below
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- ☆71Updated 10 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆52Updated last week
- ☆31Updated 5 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆30Updated 4 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- Public release☆50Updated 5 years ago
- ☆53Updated 4 years ago
- Xilinx AXI VIP example of use☆34Updated 3 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- Project repo for the POSH on-chip network generator☆44Updated last week
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆53Updated 4 years ago
- ☆26Updated 5 years ago
- ☆25Updated last year
- An integrated CGRA design framework☆87Updated this week
- Ratatoskr NoC Simulator☆24Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 7 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 3 months ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated last month
- AXI4 BFM in Verilog☆32Updated 8 years ago
- ☆63Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆60Updated 7 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- ☆43Updated 2 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- tpu-systolic-array-weight-stationary☆22Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆93Updated 4 years ago