matutani / nocgenLinks
NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
☆67Updated 5 years ago
Alternatives and similar repositories for nocgen
Users that are interested in nocgen are comparing it to the libraries listed below
Sorting:
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week
- ☆78Updated 11 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- HLS for Networks-on-Chip☆37Updated 4 years ago
- Public release☆57Updated 6 years ago
- ☆37Updated 6 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆64Updated last week
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆133Updated 7 years ago
- ☆27Updated 6 years ago
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- ☆65Updated 3 years ago
- Project repo for the POSH on-chip network generator☆51Updated 7 months ago
- ☆66Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- ☆56Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆81Updated 2 years ago
- Ratatoskr NoC Simulator☆28Updated 4 years ago
- ☆71Updated 6 years ago
- SystemVerilog modules and classes commonly used for verification☆50Updated this week
- Development of a Network on Chip Simulation using SystemC.☆33Updated 8 years ago
- SoC Based on ARM Cortex-M3☆34Updated 5 months ago
- ☆44Updated last year
- eyeriss-chisel3☆40Updated 3 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆12Updated 2 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆71Updated 4 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated 3 weeks ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆37Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆82Updated 7 years ago