NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
☆77Dec 30, 2019Updated 6 years ago
Alternatives and similar repositories for nocgen
Users that are interested in nocgen are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆14Aug 9, 2019Updated 6 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆193Nov 18, 2024Updated last year
- Network on Chip Implementation written in SytemVerilog☆209Aug 27, 2022Updated 3 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆38Dec 22, 2023Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆66Jun 10, 2026Updated last month
- A short tutorial on Gem5 with focus on how to run and modify Garnet2.0☆17Apr 18, 2018Updated 8 years ago
- ☆86Oct 25, 2014Updated 11 years ago
- A Chisel RTL generator for network-on-chip interconnects☆233Nov 7, 2025Updated 8 months ago
- A Fast, Low-Overhead On-chip Network☆319Updated this week
- EE577b-Course-Project☆19May 6, 2020Updated 6 years ago
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆21May 30, 2023Updated 3 years ago
- An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.☆38Updated this week
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆151Mar 19, 2018Updated 8 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- Ratatoskr NoC Simulator☆30Apr 13, 2021Updated 5 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 12 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆38Sep 25, 2019Updated 6 years ago
- Network on Chip Simulator☆330Jun 9, 2026Updated last month
- ☆61Aug 30, 2021Updated 4 years ago
- Public release☆59Sep 3, 2019Updated 6 years ago
- Cycle Accurate Network-on-Chip Simulator☆37Jul 11, 2026Updated 2 weeks ago
- A verilog implementation for Network-on-Chip☆85Feb 3, 2018Updated 8 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- NoC based MPSoC☆11Jul 17, 2014Updated 12 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆178Jun 18, 2020Updated 6 years ago
- CARLsim is an efficient, easy-to-use, GPU-accelerated software framework for simulating large-scale spiking neural network (SNN) models w…☆17May 17, 2022Updated 4 years ago
- SystemC/TLM-2.0 Co-simulation framework☆300Jun 26, 2026Updated last month
- ☆242Jun 25, 2025Updated last year
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Jul 17, 2023Updated 3 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 10 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- GPGPU-SIM 使用篇☆14Nov 12, 2022Updated 3 years ago
- ☆11Oct 10, 2019Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆184Dec 14, 2019Updated 6 years ago
- all kind of notes, I maybe sort this in the future☆13Aug 29, 2025Updated 10 months ago
- MMC (and derivative standards) host controller☆26Sep 14, 2020Updated 5 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 5 years ago