☆242Jun 25, 2025Updated last year
Alternatives and similar repositories for OpenNoC
Users that are interested in OpenNoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Fast, Low-Overhead On-chip Network☆319Updated this week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆193Nov 18, 2024Updated last year
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆931Jul 8, 2026Updated last week
- An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.☆38Jul 11, 2026Updated last week
- A Chisel RTL generator for network-on-chip interconnects☆233Nov 7, 2025Updated 8 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A fork of Xiangshan for AI☆54Updated this week
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆69Updated this week
- Open-source non-blocking L2 cache☆65Updated this week
- 体系结构研讨 + ysyx高阶大纲 (WIP☆216Oct 14, 2024Updated last year
- ☆15Jun 27, 2024Updated 2 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆41Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,627Updated this week
- OpenXuantie - OpenC910 Core☆1,457Jun 28, 2024Updated 2 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆246Jul 16, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆42Apr 28, 2019Updated 7 years ago
- Public release☆59Sep 3, 2019Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆622Jul 2, 2026Updated 2 weeks ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆386Jul 14, 2026Updated last week
- Network on Chip Implementation written in SytemVerilog☆209Aug 27, 2022Updated 3 years ago
- automatic-verilog based on vimscript☆290Oct 24, 2023Updated 2 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆114Oct 31, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆15Updated this week
- The official NaplesPU hardware code repository☆35Jul 27, 2019Updated 6 years ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆186Apr 15, 2026Updated 3 months ago
- ☆97Nov 12, 2025Updated 8 months ago
- AMBA AXI VIP☆467Jun 28, 2024Updated 2 years ago
- The Ultra-Low Power RISC-V Core☆1,888Aug 6, 2025Updated 11 months ago
- ☆40Jul 28, 2025Updated 11 months ago
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆34May 22, 2026Updated 2 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- "aura" my super-scalar O3 cpu core☆26May 25, 2024Updated 2 years ago
- BookSim 2.0☆445Jun 24, 2024Updated 2 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 6 years ago
- Useful UVM extensions☆28Jul 10, 2024Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated last year
- Berkeley's Spatial Array Generator☆1,402Jun 30, 2026Updated 3 weeks ago