RV-BOSC / OpenNoC
☆78Updated 2 weeks ago
Alternatives and similar repositories for OpenNoC:
Users that are interested in OpenNoC are comparing it to the libraries listed below
- An AXI4 crossbar implementation in SystemVerilog☆130Updated 2 months ago
- ☆78Updated last month
- GPGPU supporting RISCV-V, developed with verilog HDL☆79Updated 5 months ago
- ☆39Updated 2 years ago
- A Chisel RTL generator for network-on-chip interconnects☆182Updated 2 months ago
- ☆63Updated 2 years ago
- A Study of the SiFive Inclusive L2 Cache☆54Updated last year
- AXI协议规范中文翻译版☆137Updated 2 years ago
- ☆74Updated this week
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆85Updated 4 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆88Updated last year
- Vector processor for RISC-V vector ISA☆112Updated 4 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆55Updated 3 years ago
- FFT generator using Chisel☆57Updated 3 years ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆26Updated 10 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆124Updated 3 weeks ago
- An integrated CGRA design framework☆85Updated 2 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆47Updated 2 years ago
- Collect some IC textbooks for learning.☆120Updated 2 years ago
- ☆57Updated 2 months ago
- Wrapper for Rocket-Chip on FPGAs☆128Updated 2 years ago
- ☆36Updated 6 years ago
- AXI DMA 32 / 64 bits☆105Updated 10 years ago
- A Fast, Low-Overhead On-chip Network☆156Updated this week
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 6 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆118Updated last month
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆136Updated 5 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆180Updated last week