☆224Jun 25, 2025Updated 8 months ago
Alternatives and similar repositories for OpenNoC
Users that are interested in OpenNoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆37Updated this week
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆878Mar 16, 2026Updated last week
- A Fast, Low-Overhead On-chip Network☆272Updated this week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆190Nov 18, 2024Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 4 months ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Mar 13, 2026Updated last week
- 体系结构研讨 + ysyx高阶大纲 (WIP☆202Oct 14, 2024Updated last year
- Open-source non-blocking L2 cache☆55Updated this week
- ☆15Jun 27, 2024Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,519Mar 11, 2026Updated last week
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆22Apr 25, 2025Updated 10 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- Public release☆58Sep 3, 2019Updated 6 years ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆37Oct 23, 2025Updated 5 months ago
- ☆41Apr 28, 2019Updated 6 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 3 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆239Jul 16, 2023Updated 2 years ago
- An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.☆35Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆577Mar 11, 2026Updated last week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆18Feb 25, 2026Updated 3 weeks ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆344Mar 9, 2026Updated 2 weeks ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆111Oct 31, 2023Updated 2 years ago
- ☆93Nov 12, 2025Updated 4 months ago
- Network on Chip Implementation written in SytemVerilog☆197Aug 27, 2022Updated 3 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Jan 19, 2026Updated 2 months ago
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- OpenXuantie - OpenC910 Core☆1,397Jun 28, 2024Updated last year
- The Ultra-Low Power RISC-V Core☆1,774Aug 6, 2025Updated 7 months ago
- AMBA AXI VIP☆449Jun 28, 2024Updated last year
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆50Jan 2, 2025Updated last year
- ☆12Mar 12, 2026Updated last week
- "aura" my super-scalar O3 cpu core☆25May 25, 2024Updated last year
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 5 years ago
- BookSim 2.0☆410Jun 24, 2024Updated last year
- ☆13Jul 28, 2022Updated 3 years ago
- Useful UVM extensions☆27Jul 10, 2024Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated 10 months ago