RV-BOSC / OpenNoCLinks
☆214Updated 6 months ago
Alternatives and similar repositories for OpenNoC
Users that are interested in OpenNoC are comparing it to the libraries listed below
Sorting:
- An AXI4 crossbar implementation in SystemVerilog☆196Updated 3 months ago
- Collect some IC textbooks for learning.☆178Updated 3 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆133Updated 10 months ago
- ☆47Updated 3 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆234Updated 2 years ago
- AXI协议规范中文翻译版☆166Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆255Updated last week
- Some useful documents of Synopsys☆92Updated 4 years ago
- A Chisel RTL generator for network-on-chip interconnects☆223Updated last month
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆110Updated 2 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆477Updated 3 weeks ago
- CPU Design Based on RISCV ISA☆126Updated last year
- AXI总线连接器☆105Updated 5 years ago
- IC implementation of Systolic Array for TPU☆317Updated last year
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆140Updated 7 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆109Updated 5 years ago
- Network on Chip Implementation written in SytemVerilog☆196Updated 3 years ago
- ☆91Updated 2 months ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆217Updated last month
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆177Updated 6 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 3 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆121Updated 12 years ago
- Vector processor for RISC-V vector ISA☆133Updated 5 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆183Updated last year
- Network on Chip Simulator☆296Updated last month
- achieve softmax in PYNQ with heterogeneous computing.☆67Updated 7 years ago
- some knowleage about SystemC/TLM etc.☆27Updated 2 years ago
- AMBA AXI VIP☆434Updated last year