RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
☆196Nov 18, 2024Updated last year
Alternatives and similar repositories for ravenoc
Users that are interested in ravenoc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Network on Chip Implementation written in SytemVerilog☆211Aug 27, 2022Updated 3 years ago
- ☆61Aug 30, 2021Updated 4 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆156Mar 19, 2018Updated 8 years ago
- A Fast, Low-Overhead On-chip Network☆330Updated this week
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- General Purpose AXI Direct Memory Access☆80May 12, 2024Updated 2 years ago
- A Chisel RTL generator for network-on-chip interconnects☆233Nov 7, 2025Updated 9 months ago
- HLS for Networks-on-Chip☆41Feb 18, 2021Updated 5 years ago
- Network on Chip for MPSoC☆29Aug 7, 2026Updated last week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆67Jun 10, 2026Updated 2 months ago
- ☆15Jun 27, 2024Updated 2 years ago
- ☆244Jun 25, 2025Updated last year
- OpenSoC Fabric - A Network-On-Chip Generator☆178Jun 18, 2020Updated 6 years ago
- Useful UVM extensions☆28Jul 10, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 5 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆69Aug 10, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,659Aug 5, 2026Updated last week
- ☆86Oct 25, 2014Updated 11 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆25Mar 25, 2025Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆236Aug 25, 2020Updated 5 years ago
- Verilog Configurable Cache☆197Jun 10, 2026Updated 2 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆139Jul 22, 2021Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Mar 8, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- YAMM package repository☆34Mar 20, 2023Updated 3 years ago
- Parametric AXI4 crossbar in SystemVerilog☆240May 25, 2026Updated 2 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆680Jul 7, 2026Updated last month
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆38Dec 24, 2024Updated last year
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated last year
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- ☆32Feb 20, 2024Updated 2 years ago
- Common SystemVerilog components☆783Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆14Aug 9, 2026Updated last week
- An Open Source Link Protocol and Controller☆29Aug 1, 2021Updated 5 years ago
- RISC-V Nox core☆72Jul 22, 2025Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- Novel GUI Based UVM Testbench Template Builder☆156Apr 14, 2021Updated 5 years ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆469Sep 13, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,275May 29, 2026Updated 2 months ago