aignacio / ravenocLinks
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
☆185Updated last year
Alternatives and similar repositories for ravenoc
Users that are interested in ravenoc are comparing it to the libraries listed below
Sorting:
- Network on Chip Implementation written in SytemVerilog☆196Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆257Updated 2 weeks ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆140Updated 7 years ago
- An AXI4 crossbar implementation in SystemVerilog☆198Updated 4 months ago
- AXI4 and AXI4-Lite interface definitions☆99Updated 5 years ago
- AMBA bus generator including AXI, AHB, and APB☆117Updated 4 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆97Updated 6 years ago
- Verilog Configurable Cache☆187Updated last week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 2 weeks ago
- Vector processor for RISC-V vector ISA☆133Updated 5 years ago
- Altera Advanced Synthesis Cookbook 11.0☆112Updated 2 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago
- ☆170Updated 3 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆110Updated 2 years ago
- A verilog implementation for Network-on-Chip☆78Updated 7 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆275Updated 3 weeks ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆142Updated 6 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- AHB3-Lite Interconnect☆108Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 2 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last year
- General Purpose AXI Direct Memory Access☆62Updated last year
- round robin arbiter☆77Updated 11 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆135Updated last month
- AXI interface modules for Cocotb☆304Updated 3 months ago
- UVM 1.2 port to Python☆257Updated 10 months ago
- A Chisel RTL generator for network-on-chip interconnects☆223Updated last month
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆144Updated last year
- Various caches written in Verilog-HDL☆127Updated 10 years ago
- SDRAM controller with AXI4 interface☆99Updated 6 years ago