RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
☆201Nov 18, 2024Updated last year
Alternatives and similar repositories for ravenoc
Users that are interested in ravenoc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Network on Chip Implementation written in SytemVerilog☆214Aug 27, 2022Updated 4 years ago
- ☆62Aug 30, 2021Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆159Mar 19, 2018Updated 8 years ago
- A Fast, Low-Overhead On-chip Network☆362Oct 10, 2026Updated last week
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- General Purpose AXI Direct Memory Access☆82May 12, 2024Updated 2 years ago
- A Chisel RTL generator for network-on-chip interconnects☆239Nov 7, 2025Updated 11 months ago
- HLS for Networks-on-Chip☆41Feb 18, 2021Updated 5 years ago
- Network on Chip for MPSoC☆30Aug 7, 2026Updated 2 months ago
- ☆15Jun 27, 2024Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆67Aug 28, 2026Updated last month
- ☆255Jun 25, 2025Updated last year
- OpenSoC Fabric - A Network-On-Chip Generator☆179Jun 18, 2020Updated 6 years ago
- Useful UVM extensions☆28Jul 10, 2024Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆69Aug 18, 2026Updated last month
- ☆89Oct 25, 2014Updated 11 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,724Sep 24, 2026Updated 3 weeks ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 5 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆26Mar 25, 2025Updated last year
- Verilog Configurable Cache☆197Sep 21, 2026Updated 3 weeks ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆239Aug 25, 2020Updated 6 years ago
- An Open Source Link Protocol and Controller☆29Aug 1, 2021Updated 5 years ago
- YAMM package repository☆35Mar 20, 2023Updated 3 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Wavious DDR (WDDR) Physical interface (PHY) Hardware