Alternatives and similar repositories for tnoc:

Users that are interested in tnoc are comparing it to the libraries listed below

• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆157Updated 2 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆130Updated last month
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆121Updated 6 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆88Updated 4 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆112Updated 4 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆58Updated 4 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆71Updated 6 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆155Updated 3 weeks ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆103Updated 10 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆170Updated last month
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆130Updated last month
• freecores / round_robin_arbiter
  round robin arbiter
  ☆70Updated 10 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆125Updated 11 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆144Updated last year
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆93Updated 3 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆182Updated last month
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 8 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆221Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆82Updated 4 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆102Updated 3 months ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆81Updated 5 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆130Updated 3 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆116Updated 3 months ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆134Updated 6 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆247Updated 10 months ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆88Updated last year
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆369Updated 6 months ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆72Updated 12 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆55Updated 4 years ago