Alternatives and similar repositories for cde

Users that are interested in cde are comparing it to the libraries listed below

• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆244Updated last year
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 3 years ago
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆24Updated last year
• ucb-bar / testchipip
  ☆87Updated last week
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆163Updated 2 years ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆233Updated last year
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆155Updated last year
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆226Updated 3 months ago
• chipsalliance / diplomacy
  ☆23Updated 2 months ago
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆92Updated last week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆160Updated last year
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆123Updated 2 years ago
• ucb-bar / ucie
  An open-source UCIe implementation
  ☆82Updated last week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆109Updated 4 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆266Updated 3 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆128Updated 2 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆111Updated 2 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆92Updated 2 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆212Updated last year
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆56Updated last year
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆49Updated 3 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆107Updated last week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆89Updated last year
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆119Updated 3 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆192Updated last week
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆51Updated 5 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆38Updated 4 months ago