A Scala library for Context-Dependent Environments
☆51Apr 25, 2024Updated 2 years ago
Alternatives and similar repositories for cde
Users that are interested in cde are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆25Dec 4, 2025Updated 4 months ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆234Aug 19, 2024Updated last year
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆58Oct 27, 2024Updated last year
- ☆90Apr 21, 2026Updated last week
- ☆71Feb 2, 2026Updated 3 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- A Chisel RTL generator for network-on-chip interconnects☆230Nov 7, 2025Updated 5 months ago
- Lab assignments for the Agile Hardware Design course☆18Nov 14, 2025Updated 5 months ago
- The working draft to split rocket core out from rocket chip☆14Dec 22, 2023Updated 2 years ago
- The specification for the FIRRTL language☆64Apr 25, 2026Updated last week
- ☆21Mar 18, 2022Updated 4 years ago
- ☆18May 6, 2025Updated 11 months ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆20Nov 9, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Flexible Intermediate Representation for RTL☆749Aug 20, 2024Updated last year
- An RTL generator for a last-level shared inclusive TileLink cache controller☆25Jan 17, 2025Updated last year
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 3 years ago
- A template project for beginning new Chisel work☆696Feb 24, 2026Updated 2 months ago
- Digital Design with Chisel☆910Apr 16, 2026Updated 2 weeks ago
- chipyard in mill :P☆77Nov 20, 2023Updated 2 years ago
- ☆10Dec 28, 2020Updated 5 years ago
- XiangShan Frontend Develop Environment☆70Updated this week
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆20Oct 22, 2025Updated 6 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆240Nov 20, 2024Updated last year
- IOPMP IP☆25Jul 11, 2025Updated 9 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆607Aug 9, 2024Updated last year
- Chisel: A Modern Hardware Design Language☆4,644Updated this week
- A template for developing custom FIRRTL transforms☆10Jan 30, 2020Updated 6 years ago
- ☆13May 8, 2025Updated 11 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆130Mar 6, 2026Updated last month
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 7 months ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆89Mar 17, 2026Updated last month
- ☆12Jan 19, 2022Updated 4 years ago
- ☆44Dec 5, 2025Updated 4 months ago
- Full-featured, robust deriving for Caliban.☆16Aug 20, 2024Updated last year
- ☆20Mar 3, 2026Updated last month