A Scala library for Context-Dependent Environments
☆51Apr 25, 2024Updated last year
Alternatives and similar repositories for cde
Users that are interested in cde are comparing it to the libraries listed below
Sorting:
- ☆25Dec 4, 2025Updated 2 months ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆233Aug 19, 2024Updated last year
- The working draft to split rocket core out from rocket chip☆14Dec 22, 2023Updated 2 years ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆58Oct 27, 2024Updated last year
- This repository contains the implementation of RISC-V Single Cycle Cores done by Undergraduate Students by using CHISEL and Functional Pr…☆10Oct 12, 2022Updated 3 years ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 3 months ago
- ☆87Jan 30, 2026Updated last month
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- ☆18May 6, 2025Updated 9 months ago
- Lab assignments for the Agile Hardware Design course☆18Nov 14, 2025Updated 3 months ago
- ☆71Feb 2, 2026Updated last month
- Rawls service for DSDE☆26Feb 9, 2026Updated 3 weeks ago
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- The specification for the FIRRTL language☆62Updated this week
- ☆21Mar 18, 2022Updated 3 years ago
- An RTL generator for a last-level shared inclusive TileLink cache controller☆24Jan 17, 2025Updated last year
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆20Nov 9, 2022Updated 3 years ago
- An open-source UCIe implementation☆83Updated this week
- XiangShan Frontend Develop Environment☆68Updated this week
- A stream to RTL compiler based on MLIR and CIRCT☆16Nov 15, 2022Updated 3 years ago
- SBT Plugins For ZIO Projects☆12Updated this week
- ☆12May 8, 2025Updated 9 months ago
- ☆11Jan 21, 2019Updated 7 years ago
- A template for developing custom FIRRTL transforms☆10Jan 30, 2020Updated 6 years ago
- ☆12Dec 16, 2025Updated 2 months ago
- ☆15Dec 9, 2025Updated 2 months ago
- Cluster membership and failure detection☆11Oct 24, 2023Updated 2 years ago
- UUID V1, V6, V7 & TypeID generation with ZIO☆12Updated this week
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- Generic AXI interconnect fabric☆13Jul 17, 2014Updated 11 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- ☆10Dec 28, 2020Updated 5 years ago
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆20Oct 22, 2025Updated 4 months ago
- Streaming PDF processor for Scala☆13Apr 2, 2025Updated 11 months ago
- kenDryte K210 Cloud Build Support☆11Oct 24, 2018Updated 7 years ago
- ☆11Oct 23, 2023Updated 2 years ago
- Run Rocket Chip on VCU128☆30Oct 21, 2025Updated 4 months ago