Alternatives and similar repositories for CherrySprings

Users that are interested in CherrySprings are comparing it to the libraries listed below

• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆55Updated last year
• OSCPU / ysyxSoC
  ☆91Updated 2 months ago
• OSCPU / yosys-sta
  ☆87Updated last month
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• lizhirui / DreamCore
  ☆64Updated 3 years ago
• Jpz-sdju / trinity
  ☆32Updated 4 months ago
• OSCPU / chisel-playground
  ☆68Updated 10 months ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆71Updated last year
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆44Updated 2 years ago
• pulp-platform / fpu
  ☆57Updated 6 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated last year
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆73Updated 2 weeks ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆66Updated 3 years ago
• out-of-order55 / SRT-Divider
  简单的未优化的SRT除法器
  ☆12Updated last year
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆131Updated 9 months ago
• kaitoukito / YSYX-NJU-Group
  YSYX RISC-V Project NJU Study Group
  ☆16Updated 11 months ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆131Updated 5 years ago
• TYOD-SOC / RISCV-Accelerator
  ☆37Updated 7 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆47Updated 3 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆165Updated this week
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆61Updated 4 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆44Updated 2 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆51Updated 2 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆196Updated 3 months ago
• kuladeepsaireddy / OpenNoc
  ☆39Updated 6 years ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆33Updated 10 months ago
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• hyf6661669 / verilog_library
  HYF's high quality verilog codes
  ☆16Updated 11 months ago