BookSim 2.0
☆405Jun 24, 2024Updated last year
Alternatives and similar repositories for booksim2
Users that are interested in booksim2 are comparing it to the libraries listed below
Sorting:
- BookSim 1.0☆25Mar 22, 2014Updated 11 years ago
- Network on Chip Simulator☆305Oct 26, 2025Updated 4 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆189Jan 8, 2026Updated 2 months ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆257Oct 6, 2022Updated 3 years ago
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆451Aug 3, 2024Updated last year
- Netrace: a network packet trace reader☆14Jun 16, 2014Updated 11 years ago
- ☆377May 11, 2023Updated 2 years ago
- A pre-RTL, power-performance model for fixed-function accelerators☆186Jan 17, 2024Updated 2 years ago
- Repository to host and maintain SCALE-Sim code☆417Feb 2, 2026Updated last month
- DRAMSim2: A cycle accurate DRAM simulator☆294Nov 11, 2020Updated 5 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆75Jul 25, 2025Updated 7 months ago
- ASTRA-sim2.0: Modeling Hierarchical Networks and Disaggregated Systems for Large-model Training at Scale☆524Jan 3, 2026Updated 2 months ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆342Feb 16, 2026Updated 2 weeks ago
- ☆59Jun 3, 2025Updated 9 months ago
- A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …☆681Aug 29, 2023Updated 2 years ago
- An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model☆531Jun 25, 2024Updated last year
- GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for…☆1,578Feb 15, 2025Updated last year
- A fast and scalable x86-64 multicore simulator☆388Nov 27, 2023Updated 2 years ago
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆504Feb 4, 2026Updated last month
- Fast and accurate DRAM power and energy estimation tool☆189Updated this week
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Nov 2, 2015Updated 10 years ago
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 4 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆148Jun 16, 2025Updated 8 months ago
- Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.☆460Feb 19, 2026Updated 2 weeks ago
- cycle accurate Network-on-Chip Simulator☆33Jan 4, 2026Updated 2 months ago
- This is the top-level repository for the Accel-Sim framework.☆566Feb 15, 2026Updated 3 weeks ago
- The Sniper Multi-Core Simulator☆165Oct 18, 2025Updated 4 months ago
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆105Feb 22, 2023Updated 3 years ago
- A heterogeneous architecture timing model simulator.☆175Sep 11, 2025Updated 5 months ago
- Synthetic Traffic Models Capturing a Full Range of Cache Coherent Behaviour☆14May 17, 2019Updated 6 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆50Jan 2, 2025Updated last year
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆214Aug 8, 2020Updated 5 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆72Dec 29, 2025Updated 2 months ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆21Dec 10, 2018Updated 7 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Apr 30, 2019Updated 6 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆156May 26, 2025Updated 9 months ago
- The official repository for the gem5 computer-system architecture simulator.☆2,494Updated this week
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆82Mar 12, 2025Updated 11 months ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆875Updated this week