amonemi / ProNoC
Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
☆48Updated 5 months ago
Related projects ⓘ
Alternatives and complementary repositories for ProNoC
- ☆26Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆44Updated 3 years ago
- ☆67Updated 10 years ago
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- ☆47Updated 3 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆56Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆56Updated 10 months ago
- A verilog implementation for Network-on-Chip☆67Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year
- eyeriss-chisel3☆39Updated 2 years ago
- ☆25Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆68Updated 6 years ago
- SoC Based on ARM Cortex-M3☆25Updated 6 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆43Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆58Updated last month
- HLS for Networks-on-Chip☆31Updated 3 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables …☆28Updated 4 years ago
- ☆37Updated 5 years ago
- round robin arbiter☆68Updated 10 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆63Updated last year
- AXI4 and AXI4-Lite interface definitions☆83Updated 4 years ago
- The memory model was leveraged from micron.☆19Updated 6 years ago
- This is a tutorial on standard digital design flow☆73Updated 3 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆41Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆137Updated 3 weeks ago
- Ratatoskr NoC Simulator☆21Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆71Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆83Updated 4 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago