amonemi / ProNoCLinks
Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
☆60Updated 3 weeks ago
Alternatives and similar repositories for ProNoC
Users that are interested in ProNoC are comparing it to the libraries listed below
Sorting:
- ☆40Updated 6 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- ☆67Updated 3 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- A verilog implementation for Network-on-Chip☆79Updated 7 years ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- ☆80Updated 11 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆141Updated 7 years ago
- SoC Based on ARM Cortex-M3☆36Updated 7 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- round robin arbiter☆77Updated 11 years ago
- An AXI4 crossbar implementation in SystemVerilog☆201Updated 4 months ago
- SystemVerilog modules and classes commonly used for verification☆54Updated last week
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated 2 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago
- ☆70Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆185Updated last year
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- This is a tutorial on standard digital design flow☆82Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆77Updated last month
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- Implementing Different Adder Structures in Verilog☆76Updated 6 years ago
- Network on Chip Implementation written in SytemVerilog☆196Updated 3 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆23Updated 2 years ago
- ☆31Updated 5 years ago
- BlackParrot on Zynq☆47Updated 3 weeks ago
- AMBA bus generator including AXI, AHB, and APB☆117Updated 4 years ago