Alternatives and similar repositories for chisel-formal

Users that are interested in chisel-formal are comparing it to the libraries listed below

• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆49Updated 2 weeks ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 5 months ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 4 months ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆79Updated last year
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆26Updated 9 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆89Updated last year
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 4 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆76Updated last year
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year
• TsaiAnson / verif
  ☆12Updated 4 years ago
• iscas-tis / CHA
  ☆19Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆88Updated last week
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆50Updated 11 months ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 4 years ago
• efeslab / hardware-bugbase
  ☆19Updated last year
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆17Updated 6 years ago
• chipsalliance / espresso
  ☆41Updated 4 months ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated last month
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆156Updated 11 months ago
• sterin / super-prove-build
  ☆13Updated 5 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆156Updated last week
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 8 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 2 months ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆47Updated 2 weeks ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆108Updated 5 months ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆58Updated 11 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆43Updated 2 years ago